公开(公告)号：US20120129288A1

公开(公告)日：2012-05-24

申请号：US13361998

申请日：2012-01-31

申请人： Satoshi KOBAYASHI ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Satoshi KOBAYASHI ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L33/08 ,  H01L21/336

CPC分类号： H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

摘要翻译： 一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及具有高批量生产率的显示装置的制造方法。 在包括反交错通道停止型薄膜晶体管的显示装置中，反交错通道停止型薄膜晶体管包括包含沟道形成区的微晶半导体膜，以及含有杂质元素的杂质区 在微晶半导体膜的沟道形成区域中，在不与源极和漏极重叠的区域中选择性地提供一种导电型。

公开(公告)号：US08133771B2

公开(公告)日：2012-03-13

申请号：US12838115

申请日：2010-07-16

申请人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L21/00

CPC分类号： H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

摘要翻译： 一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及具有高批量生产率的显示装置的制造方法。 在包括反交错通道停止型薄膜晶体管的显示装置中，反交错通道停止型薄膜晶体管包括包含沟道形成区的微晶半导体膜，以及含有杂质元素的杂质区 在微晶半导体膜的沟道形成区域中，在不与源极和漏极重叠的区域中选择性地提供一种导电型。

公开(公告)号：US08389993B2

公开(公告)日：2013-03-05

申请号：US13361998

申请日：2012-01-31

申请人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L27/12

CPC分类号： H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

摘要翻译： 一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及具有高批量生产率的显示装置的制造方法。 在包括反交错通道停止型薄膜晶体管的显示装置中，反交错通道停止型薄膜晶体管包括包含沟道形成区的微晶半导体膜，以及含有杂质元素的杂质区 在微晶半导体膜的沟道形成区域中，在不与源极和漏极重叠的区域中选择性地提供一种导电型。

公开(公告)号：US07768009B2

公开(公告)日：2010-08-03

申请号：US12196798

申请日：2008-08-22

申请人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L27/12

CPC分类号： H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

摘要翻译： 一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及具有高批量生产率的显示装置的制造方法。 在包括反交错通道停止型薄膜晶体管的显示装置中，反交错通道停止型薄膜晶体管包括包含沟道形成区的微晶半导体膜，以及含有杂质元素的杂质区 在微晶半导体膜的沟道形成区域中，在不与源极和漏极重叠的区域中选择性地提供一种导电型。

公开(公告)号：US20090152559A1

公开(公告)日：2009-06-18

申请号：US12326661

申请日：2008-12-02

申请人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

发明人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78609

摘要： A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured.

摘要翻译： 提供了薄膜晶体管的制造方法和使用少量掩模的显示装置。 堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜。 然后，使用多色调掩模在其上形成具有凹部的抗蚀剂掩模。 进行第一蚀刻以形成薄膜堆叠体，并且进行薄膜叠层体被侧蚀刻的第二蚀刻以形成栅极电极层。 使抗蚀剂后退，然后形成源电极，漏电极等; 因此，制造薄膜晶体管。

公开(公告)号：US08101442B2

公开(公告)日：2012-01-24

申请号：US12390264

申请日：2009-02-20

申请人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Atsushi Umezaki

发明人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Atsushi Umezaki

IPC分类号： H01L21/00 ,  H01L21/04 ,  H01L21/14 ,  H01L21/15 ,  H01L31/036

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3262

摘要： A manufacture process of a thin film transistor mounted on an EL display device is simplified. A thin film transistor is manufactured by stacking a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; forming a first resist mask over the stacked films; performing first etching to form a thin-film stack body; performing second etching by side etching is conducted on the thin-film stack body to form a gate electrode layer; and forming a source and drain electrode layer and the like with use of a second resist mask. An EL display device is manufactured using the thin film transistor.

摘要翻译： 安装在EL显示装置上的薄膜晶体管的制造工艺简化。 通过堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜来制造薄膜晶体管; 在堆叠的膜上形成第一抗蚀剂掩模; 执行第一蚀刻以形成薄膜堆叠体; 在薄膜堆叠体上进行侧蚀刻进行第二蚀刻，形成栅电极层; 以及使用第二抗蚀剂掩模形成源极和漏极电极层等。 使用薄膜晶体管制造EL显示装置。

公开(公告)号：US07993991B2

公开(公告)日：2011-08-09

申请号：US12326661

申请日：2008-12-02

申请人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

发明人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

IPC分类号： H01L21/00 ,  G02F1/136

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78609

摘要： A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured.

摘要翻译： 提供了薄膜晶体管的制造方法和使用少量掩模的显示装置。 堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜。 然后，使用多色调掩模在其上形成具有凹部的抗蚀剂掩模。 进行第一蚀刻以形成薄膜堆叠体，并且进行薄膜叠层体被侧蚀刻的第二蚀刻以形成栅极电极层。 使抗蚀剂后退，然后形成源电极，漏电极等; 因此，制造薄膜晶体管。

公开(公告)号：US20090224249A1

公开(公告)日：2009-09-10

申请号：US12390264

申请日：2009-02-20

申请人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Atsushi Umezaki

发明人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Atsushi Umezaki

IPC分类号： H01L29/04 ,  H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3262

摘要： A manufacture process of a thin film transistor mounted on an EL display device is simplified. A thin film transistor is manufactured by stacking a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; forming a first resist mask over the stacked films; performing first etching to form a thin-film stack body; performing second etching by side etching is conducted on the thin-film stack body to form a gate electrode layer; and forming a source and drain electrode layer and the like with use of a second resist mask. An EL display device is manufactured using the thin film transistor.

摘要翻译： 安装在EL显示装置上的薄膜晶体管的制造工艺简化。 通过堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜来制造薄膜晶体管; 在堆叠的膜上形成第一抗蚀剂掩模; 执行第一蚀刻以形成薄膜堆叠体; 在薄膜堆叠体上进行侧蚀刻进行第二蚀刻，形成栅电极层; 以及使用第二抗蚀剂掩模形成源极和漏极电极层等。 使用薄膜晶体管制造EL显示装置。

公开(公告)号：US09196633B2

公开(公告)日：2015-11-24

申请号：US12556704

申请日：2009-09-10

申请人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

发明人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

IPC分类号： H01L33/00 ,  H01L27/12 ,  G02F1/1362 ,  H01L27/02 ,  H01L29/786

CPC分类号： H01L27/124 ,  G02F1/136204 ,  G02F1/136286 ,  H01L27/0266 ,  H01L27/1225 ,  H01L29/7869

摘要： A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

摘要翻译： 保护电路包括非线性元件，其包括栅电极，覆盖栅电极的栅极绝缘层，与栅极绝缘层上的栅电极重叠的第一氧化物半导体层，以及第一布线层和第二布线层 其端部与第一氧化物半导体层上的栅电极重叠，并且其中层叠有导电层和第二氧化物半导体层。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。

公开(公告)号：US08389988B2

公开(公告)日：2013-03-05

申请号：US12571554

申请日：2009-10-01

申请人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

发明人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

IPC分类号： H01L28/72

CPC分类号： G02F1/136204 ,  H01L27/0248 ,  H01L27/1225 ,  H01L27/124 ,  H01L33/0041 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to take advantage of the properties of a display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area are necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer over the gate insulating film; a channel protective layer covering a region which overlaps with a channel formation region of the first oxide semiconductor layer; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and over the first oxide semiconductor layer. The gate electrode is connected to a scan line or a signal line, the first wiring layer or the second wiring layer is directly connected to the gate electrode.