公开(公告)号：US06819598B2

公开(公告)日：2004-11-16

申请号：US10605765

申请日：2003-10-24

申请人： Satoshi Yamazaki ,  Tetsu Kubota ,  Norio Fujita

发明人： Satoshi Yamazaki ,  Tetsu Kubota ,  Norio Fujita

IPC分类号： G11C700

CPC分类号： G11C16/20 ,  G11C2029/4402

摘要： A memory module is described having a memory array storing data, an ID information output circuit for outputting ID information for identifying memory modules, and output switching means for selectively switching between output from the memory array and output from the ID information output circuit, and output from the ID information output circuit will be selected instead of output from the memory array until the memory module is initially written after the power supply to the memory module has been started. This enables a memory module to be identified without having to add parts to a computer system unit or providing a ROM storing a specification or the like to the memory module.

摘要翻译： 描述了具有存储数据的存储器阵列的存储器模块，用于输出用于识别存储器模块的ID信息的ID信息输出电路，以及用于选择性地切换来自存储器阵列的输出和从ID信息输出电路输出的输出切换装置，并且输出 将从ID信息输出电路中选择来自存储器阵列的输出，直到在已经开始向存储器模块供电之后，最初写存储器模块。 这使得能够识别存储器模块，而不必向计算机系统单元添加部件，或者向存储器模块提供存储规范等的ROM。

公开(公告)号：US07237105B2

公开(公告)日：2007-06-26

申请号：US10841902

申请日：2004-05-07

申请人： Norio Fujita ,  Masahiro Murakami

发明人： Norio Fujita ,  Masahiro Murakami

IPC分类号： G06F9/445 ,  G06F15/177

CPC分类号： G06F9/4406

摘要： A startup system using a boot code includes an external memory storing a boot code, a buffer connected to an external memory for storing the boot code transferred from the external memory, a DMA controller for commanding transfer of the boot code from the external memory to the buffer, and a mapping circuit connected to the buffer for mapping the boot code stored in the buffer onto a CPU. Accordingly, a flash ROM for storing the boot code may be eliminated, thereby reducing system cost.

摘要翻译： 使用引导代码的启动系统包括存储引导代码的外部存储器，连接到外部存储器的缓冲器，用于存储从外部存储器传送的引导代码的DMA控制器，用于命令将引导代码从外部存储器传送到 缓冲器和连接到缓冲器的映射电路，用于将存储在缓冲器中的引导代码映射到CPU。 因此，可以消除用于存储引导代码的闪存ROM，从而降低系统成本。

公开(公告)号：US4814208A

公开(公告)日：1989-03-21

申请号：US105758

申请日：1987-10-07

申请人： Shizuo Miyazaki ,  Norio Fujita

发明人： Shizuo Miyazaki ,  Norio Fujita

IPC分类号： B05D7/14 ,  B05D1/36 ,  B05D1/38 ,  B05D5/06 ,  B05D7/24 ,  C09C1/00 ,  C09C1/24 ,  C09D5/36 ,  B05D7/00

CPC分类号： C09C1/0021 ,  B05D5/068 ,  C09C1/0015 ,  C09C1/245 ,  C09D5/36 ,  C01P2004/20 ,  C01P2004/51 ,  C01P2004/86 ,  C01P2006/60 ,  C01P2006/65 ,  C01P2006/66 ,  C09C2200/1004 ,  C09C2200/301 ,  C09C2200/308

摘要： Disclosed is a coating method comprising the steps of applying a color coating composition, applying a coating composition containing a pigment capable of producing a metallic effect to the layer of the color coating composition and applying a clear coating composition to the layer of the pigment-containing coating composition, characterized in that the color coating composition is able to form a layer having a Munsell value of 0 to 6; that the pigment-containing coating composition contains an iron oxide pigment and a vehicle as main components, the iron oxide pigment being iron oxide particles which contain at least 80% by weight of .alpha.-iron oxide crystals and which are each coated with titanium dioxide; that about 90% by weight or more of the iron oxide pigment has a longitudinal size of about 30 .mu.m or less than 40% by weight or more of the pigment has a longitudinal size of about 5 to about 15 .mu.m; that the thickness of the pigment is about 1/10 to about 1/20 of the longitudinal size of the pigment; and that the amount of the pigment is about 0.1 to about 30 parts by weight per 100 parts by weight of the vehicle (as solids).

摘要翻译： 公开了一种涂布方法，其包括以下步骤：施加彩色涂料组合物，将含有能够产生金属效果的颜料的涂料组合物施加到彩色涂料组合物的层上，并将透明涂料组合物施涂到含颜料的层 涂料组合物，其特征在于，所述着色涂料组合物能够形成孟塞尔值为0至6的层; 含颜料的涂料组合物含有氧化铁颜料和载体作为主要成分，氧化铁颜料是氧化铁颗粒，其含有至少80重量％的α-氧化铁晶体，并且各自涂覆有二氧化钛; 约90重量％以上的氧化铁颜料的纵向尺寸为约30μm或小于40重量％或更多，颜料的纵向尺寸为约5至约15μm; 颜料的厚度为颜料的纵向尺寸的约1/10至约1/20; 并且颜料的量为每100重量份载体（固体）为约0.1至约30重量份。

公开(公告)号：US07843742B2

公开(公告)日：2010-11-30

申请号：US11996544

申请日：2006-07-26

申请人： Toshio Sunaga ,  Norio Fujita

发明人： Toshio Sunaga ,  Norio Fujita

IPC分类号： G11C7/10

CPC分类号： G11C7/22 ,  G11C8/10 ,  G11C11/4076 ,  G11C2207/2218

摘要： The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a write address, a timing of writing the write data being latched by said write latching circuit into the activated memory cell.

摘要翻译： 本发明涉及包括存储单元阵列并连接到地址输入，命令输入和数据输入/输出的存储器系统，所述存储器系统包括用于锁存读取地址的锁存电路（RALTH和WALTH）和 写地址从地址输入输入，地址选择电路（ACOMSEL），用于选择锁存在锁存电路中的读地址和写地址中的任何一个作为访问地址，用于锁存的读锁存电路（PFLTH） 从存储单元阵列读取的读取数据，用于锁存从数据输入/输出输入的写入数据的写入锁存电路（DINLTH）和用于控制由所述地址选择电路选择的存取地址的控制电路（ACTL） 响应于从所述命令输入输入的命令，所述控制电路用于控制与所选择的访问地址对应的存储单元是否被激活，并且进一步选择所述ac 写入地址是写入地址，写入被写入锁存电路的写入数据写入激活的存储单元的定时。

公开(公告)号：US07298789B2

公开(公告)日：2007-11-20

申请号：US10773361

申请日：2004-02-06

申请人： Hiroaki Kubo ,  Norio Fujita

发明人： Hiroaki Kubo ,  Norio Fujita

IPC分类号： H04L27/10

CPC分类号： H04L27/32 ,  H04B14/008

摘要： Wireless data communication method and apparatus using two electromagnetic signals having different polarizations. Codes related to relative values of the amplitudes of the two signals are generated in correspondence with data to be transmitted. The signals are modulated according to the codes using phase shift keying and amplitude shift keying. The amplitude shift keying modulates the two electromagnetic signals by changing the difference between their two amplitudes in accordance with data encodings. The two signals are transmitted to receiver, which decodes the phases and relative amplitudes to obtain the codes, and reproduces the data from the obtained codes.

摘要翻译： 使用具有不同偏振的两个电磁信号的无线数据通信方法和装置。 与两个信号的幅度的相对值相关的代码是与要发送的数据相对应地产生的。 根据代码使用相移键控和幅移键控对信号进行调制。 幅度键控通过根据数据编码改变其两个幅度之间的差异来调制两个电磁信号。 这两个信号被发送到接收机，其解码相位和相对幅度以获得代码，并且从获得的代码再现数据。

公开(公告)号：US06735713B1

公开(公告)日：2004-05-11

申请号：US09521544

申请日：2000-03-09

申请人： Norio Fujita ,  Mashahiro Murakami ,  Yoshifumi Sakamoto

发明人： Norio Fujita ,  Mashahiro Murakami ,  Yoshifumi Sakamoto

IPC分类号： G06F104

CPC分类号： G06F13/405

摘要： The present invention is directed to a microprocessor (MPU) 10 comprising a bridge chip 12 including a bus retry output part (40) for outputting a bus retry (BRTY) signal; a bus retry detection part (30) for determining whether a bus retry signal is input from the bridge chip 12; and a bus cycle controller (38) for suspending a currently executed bus cycle in response to detection of the bus retry signal and for re-starting the suspended bus cycle. The bridge chip also preferably includes an interrupt detection part (32) for determining whether another process request is issued during suspension of the bus cycle; and an interrupt controller (38) for executing that other process before re-starting the suspended bus cycle.

摘要翻译： 本发明涉及一种微处理器（MPU）10，其包括桥接芯片12，桥接芯片12包括用于输出总线重试（BRTY）信号的总线重试输出部分（40） 用于确定总线重试信号是否从桥芯片12输入的总线重试检测部分（30）; 以及一个总线周期控制器（38），用于响应于总线重试信号的检测和暂停总线周期重新启动暂停当前执行的总线周期。 桥接芯片还优选地包括用于在暂停总线周期期间确定是否发出另一个处理请求的中断检测部分（32） 以及用于在重新启动暂停的总线周期之前执行该另一进程的中断控制器（38）。

公开(公告)号：US5545295A

公开(公告)日：1996-08-13

申请号：US218043

申请日：1994-03-25

申请人： Norio Fujita ,  Hiroshi Iwata ,  Haruyoshi Fujiwara

发明人： Norio Fujita ,  Hiroshi Iwata ,  Haruyoshi Fujiwara

IPC分类号： D21F2/00 ,  D21F3/04 ,  D21G9/00 ,  D21F3/00

CPC分类号： D21G9/0063 ,  D21F2/00 ,  D21F3/04

摘要： A web transfer system is disclosed which comprises an endless belt which has a first surface which is elastic and which is structured and arranged to come into direct contact with a web in a press section and a second surface which is not in contact with the web. The endless belt has an inner core, which is located between the first surface and the second surface. The inner core is made from a material which is less elastic than the first surface. The web transfer system also comprises a hard roll and at least one pressure roll which presses the endless belt into direct contact against the hard roll. When the endless belt is pressed against the hard roll, it is deformed so as to doff the web from the hard roll directly and convey the web with the endless belt. No suction force is imposed on the endless belt.

摘要翻译： 公开了一种纸幅传送系统，其包括环形带，该环带具有弹性的第一表面，其被构造和布置成在压榨部中与纸幅直接接触，并且与纸幅不接触的第二表面。 环形带具有位于第一表面和第二表面之间的内芯。 内芯由比第一表面弹性小的材料制成。 纸幅传送系统还包括硬卷和至少一个压力辊，其将环形带压直接与硬卷直接接触。 当环形带被压靠在硬卷上时，其变形，从而直接从硬辊上脱落纤维网，并使带状物与环带传送。 环形带上没有吸力。

公开(公告)号：US09376577B2

公开(公告)日：2016-06-28

申请号：US13521800

申请日：2011-01-13

申请人： Hiroshi Shimizu ,  Norio Fujita

发明人： Hiroshi Shimizu ,  Norio Fujita

IPC分类号： B05D1/36 ,  C09D1/00 ,  C09D7/12 ,  C09C1/36 ,  C09C1/40 ,  C09C1/64 ,  C08K3/22

CPC分类号： C09D7/1216 ,  C01P2006/62 ,  C01P2006/65 ,  C08K3/22 ,  C09C1/36 ,  C09C1/3684 ,  C09C1/40 ,  C09C1/64 ,  C09D7/1266 ,  C09D7/1275 ,  C09D7/61 ,  C09D7/67 ,  C09D7/68

摘要： The present invention relates to a coating composition containing a colored aluminum pigment and a titanium oxide pigment, wherein in the case where a coating film formed from the coating composition is illuminated at 45 degrees with respect to the surface of the coating film, a ratio of lightness L* of light observed at 45 degrees with respect to specularly reflected light, relative to lightness L* of light observed at 110 degrees with respect to specularly reflected light is within a range of 1.00 to 1.50. The invention further relates to a method for forming a coating film, including steps of applying the above-described coating composition to a substrate; and further applying a clear coating composition thereto.

摘要翻译： 本发明涉及一种含有着色铝颜料和氧化钛颜料的涂料组合物，其中在由涂料组合物形成的涂膜相对于涂膜表面以45度照射的情况下， 相对于镜面反射光，在相对于镜面反射光110度观察到的光的亮度L *相对于镜面反射光观察到的光的亮度L *在1.00〜1.50的范围内。 本发明还涉及一种形成涂膜的方法，包括将上述涂料组合物涂布在基材上的步骤; 并进一步向其施加透明涂料组合物。

公开(公告)号：US20100061156A1

公开(公告)日：2010-03-11

申请号：US11996544

申请日：2006-07-26

申请人： Toshio Sunaga ,  Norio Fujita

发明人： Toshio Sunaga ,  Norio Fujita

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C8/10 ,  G11C11/4076 ,  G11C2207/2218

摘要： The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a write address, a timing of writing the write data being latched by said write latching circuit into the activated memory cell.

摘要翻译： 本发明涉及包括存储单元阵列并连接到地址输入，命令输入和数据输入/输出的存储器系统，所述存储器系统包括用于锁存读取地址的锁存电路（RALTH和WALTH）和 写地址从地址输入输入，地址选择电路（ACOMSEL），用于选择锁存在锁存电路中的读地址和写地址中的任何一个作为访问地址，用于锁存的读锁存电路（PFLTH） 从存储单元阵列读取的读取数据，用于锁存从数据输入/输出输入的写入数据的写入锁存电路（DINLTH）和用于控制由所述地址选择电路选择的存取地址的控制电路（ACTL） 响应于从所述命令输入输入的命令，所述控制电路用于控制与所选择的访问地址对应的存储单元是否被激活，并且进一步选择所述ac 写入地址是写入地址，写入被写入锁存电路的写入数据写入激活的存储单元的定时。

公开(公告)号：US20080320236A1

公开(公告)日：2008-12-25

申请号：US11767882

申请日：2007-06-25

申请人： Makoto Ueda ,  Kenichi Tsuchiya ,  Takeo Nakada ,  Norio Fujita

发明人： Makoto Ueda ,  Kenichi Tsuchiya ,  Takeo Nakada ,  Norio Fujita

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0811 ,  G06F12/0813

摘要： A system includes processor units, caches, memory shared by the processor units, a system bus interface, and a cache snoop interfaces. Each processor unit has one of the caches. The system bus interface communicatively connects the processor units to the memory via at least the caches, and is a non-cache snoop system bus interface. The cache snoop interface communicatively connects the caches, and is independent of the system bus interface. Upon a given processor unit writing a new value to an address within the memory such that the new value and the address are cached within the cache of the given processor unit a write invalidation event is sent over the cache snoop interface to the caches of the processor units other than the given processor unit. This event invalidates the address as stored within any of the caches other than the cache of the given processor unit.

摘要翻译： 系统包括处理器单元，高速缓存，由处理器单元共享的存储器，系统总线接口和高速缓存监听接口。 每个处理器单元都有一个高速缓存。 系统总线接口至少通过高速缓存通信地将处理器单元连接到存储器，并且是非高速缓存监听系统总线接口。 缓存监听接口通信地连接高速缓存，并且独立于系统总线接口。 在给定处理器单元向存储器中的地址写入新值使得新值和地址被缓存在给定处理器单元的高速缓存内时，写无效事件通过高速缓存侦听接口发送到处理器的高速缓存 单位除了给定的处理器单位。 该事件将存储在除了给定处理器单元的高速缓存之外的任何高速缓存中的地址无效。