公开(公告)号：US06861269B2

公开(公告)日：2005-03-01

申请号：US10245371

申请日：2002-09-18

申请人： Takayoshi Kawai ,  Kazuo Mitsui ,  Seigo Kodama

发明人： Takayoshi Kawai ,  Kazuo Mitsui ,  Seigo Kodama

IPC分类号： H05K13/04 ,  G05B19/418 ,  H01L21/66 ,  H01L23/544 ,  H05K1/02 ,  H05K3/00

CPC分类号： H01L22/20 ,  G05B19/4183 ,  G05B2219/32049 ,  G05B2219/45031 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/014 ,  H05K1/0269 ,  H05K3/00 ,  Y02P90/10 ,  Y10T29/41 ,  H01L2924/00

摘要： A method of fabricating an electric circuit, including first and second working processes of performing respective first and second working operations on a circuit substrate, where3in the first working process includes a first substrate-identifying step of obtaining substrate identifying information identifying the substrate on which the first working operation is to be performed, a specific-information obtaining step of recognizing a specific-information providing portion of the substrate, to obtain specific information indicating at least one specific characteristic of the substrate, a first working step of performing the first working operation on the basis of the obtained specific information, and a specific-information storing step of storing the specific information in relation to the substrate identifying information, and the second working process includes a second substrate-identifying step of obtaining the substrate identifying information identifying the substrate on which the second working operation is to be performed, and a second working step of performing the second working operation on the basis of the specific information stored in relation to the substrate identifying information. Also disclosed are electric-circuit fabricating system and control program suitable to practice the method.

摘要翻译： 一种制造电路的方法，包括在电路基板上执行各自的第一和第二工作操作的第一和第二工作过程，其中在第一工作过程中包括第一衬底识别步骤，用于获得标识衬底的衬底识别信息， 要执行第一工作操作，特定信息获取步骤，识别衬底的特定信息提供部分，以获得指示衬底的至少一个特定特性的特定信息;执行第一工作操作的第一工作步骤 基于所获得的具体信息，以及特定信息存储步骤，用于存储关于衬底识别信息的特定信息，并且第二工作过程包括第二衬底识别步骤，获得识别衬底的衬底识别信息 在哪 执行第二工作操作，以及第二工作步骤，基于与衬底识别信息相关的存储的特定信息执行第二工作操作。 还公开了适用于实施该方法的电路制造系统和控制程序。

公开(公告)号：US06885905B2

公开(公告)日：2005-04-26

申请号：US10245365

申请日：2002-09-18

申请人： Seigo Kodama ,  Takayoshi Kawai ,  Kazuo Mitsui

发明人： Seigo Kodama ,  Takayoshi Kawai ,  Kazuo Mitsui

IPC分类号： H05K13/04 ,  H01L21/00 ,  H05K1/02 ,  H05K3/00 ,  H05K13/08 ,  G06F19/00

CPC分类号： H01L21/67294 ,  H01L21/67276 ,  H05K1/0266 ,  H05K1/0269 ,  H05K3/0008 ,  H05K2201/09918 ,  H05K2201/09927

摘要： An electric-circuit fabricating system for fabricating an electric circuit, by performing a working operation on a circuit substrate, including a substrate holding device to hold the substrate, an imaging device to image a surface of the substrate on which the working operation is to be performed, an imaging control device to control the imaging device to take an image of a substrate-position fiducial mark provided on the substrate, and obtaining substrate-position information on the basis of the image, and a working device to perform the working operation on the substrate, on the basis of the substrate-position information, and wherein the imaging control device is operable to control the imaging device to take an image of a substrate ID mark provided on the substrate as held by the substrate holding device, for obtaining substrate identifying information identifying the substrate, on the basis of the image of the substrate ID mark. Also disclosed are a method and a control program for fabricating an electric circuit by performing the working operation on the substrate.

摘要翻译： 一种用于制造电路的电路制造系统，通过对包括用于保持基板的基板保持装置的电路基板执行工作操作，成像装置对要进行工作操作的基板的表面进行成像 执行成像控制装置，用于控制成像装置拍摄设置在基板上的基板位置基准标记的图像，并且基于图像获得基板位置信息;以及工作装置，用于对 所述基板基于所述基板位置信息，并且其中所述成像控制装置可操作以控制所述成像装置拍摄由所述基板保持装置保持在所述基板上的基板ID标记的图像，以获得基板 基于基板ID标记的图像识别识别基板的信息。 还公开了一种通过在基板上进行加工操作来制造电路的方法和控制程序。

公开(公告)号：US06850855B2

公开(公告)日：2005-02-01

申请号：US10265411

申请日：2002-10-07

申请人： Takayoshi Kawai ,  Kazuo Mitsui

发明人： Takayoshi Kawai ,  Kazuo Mitsui

IPC分类号： G01N21/93 ,  G01N21/956 ,  H05K13/08 ,  G01N37/00

CPC分类号： H05K13/08

摘要： Where a result of operations to mount electronic components is inspected, for example, an operating procedure of an inspecting operation is determined on the basis of mounting-condition information such as used-device information relating to used suction nozzles, feeders and other devices, and mounting-result information such as information relating to recovery actions. The operating procedure may be determined on the basis of device-usage historical information as well. For instance, the inspection operation is performed on inspecting objects selected from the mounting objects, such as mounting objects mounted with nozzles of high mounting defect ratios, mounting objects mounted with feeders of long use, etc. Additional inspecting objects are selected such that the inspection can be effected within a predetermined time. The inspecting order may be determined so as to complete the inspection in a shortest possible time.

摘要翻译： 在检查安装电子部件的操作结果的情况下，例如，基于与使用的吸嘴，馈线等装置有关的使用设备信息等安装条件信息来确定检查动作的操作程序，以及 安装结果信息，例如与恢复动作有关的信息。 操作过程也可以基于设备使用历史信息来确定。 例如，对从安装对象中选择的物体进行检查，例如安装有高安装缺陷比率的喷嘴的安装对象，安装有长期使用的进料器的安装对象等进行检查操作。选择附加的检查对象，使得检查 可以在预定时间内实现。 可以确定检查顺序，以便在最短的时间内完成检查。

公开(公告)号：US20050151525A1

公开(公告)日：2005-07-14

申请号：US11034884

申请日：2005-01-14

申请人： Yuri Komori ,  Kazuo Mitsui

发明人： Yuri Komori ,  Kazuo Mitsui

IPC分类号： H01L27/04 ,  G05F1/40 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H02M3/137 ,  H02M3/155 ,  H02M3/158

CPC分类号： H01L27/0623 ,  H01L27/0821 ,  H02M3/1588 ,  Y02B70/1466

摘要： In a semiconductor integrated circuit for a DC-DC converter, an nMOS-type transistor Qn of a CMOS inverter 1c constituting a driver 1 is electrically floated from a substrate 12 through an n-type well region 11. Thus, the nMOS-type transistor Qn is electrically insulated from other transistors such as an npn-type transistor Q1 and an L-pnp-type transistor Q2 constituting a feedback control system 9 through the n-type well region 11. Stable operation is performed with a minute current without producing a malfunction caused by the influence of a parasitic current, even if the drain potential of an nMOS-type transistor is reduced to the ground potential or lower at the time of switching by a driver constituted from a CMOS inverter, to facilitate lower power consumption and higher efficiency, and also to eliminate a constraint on layout design of components.

摘要翻译： 在用于DC-DC转换器的半导体集成电路中，构成驱动器1的CMOS反相器1c的nMOS型晶体管Qn通过n型阱区域11从衬底12浮置。因此，nMOS型 晶体管Qn通过n型阱区域11与构成反馈控制系统9的npn型晶体管Q 1和L-pnp型晶体管Q 2等其它晶体管电绝缘。以微小电流 即使在由CMOS反相器构成的驱动器切换时nMOS型晶体管的漏极电位降低到接地电位以下时，也不会产生由寄生电流的影响引起的故障，便于低功率 消耗和更高的效率，也消除了组件布局设计的约束。

公开(公告)号：US4385795A

公开(公告)日：1983-05-31

申请号：US214907

申请日：1980-12-10

申请人： Seiji Endoh ,  Shotaro Tada ,  Toru Kuga ,  Yasuo Takeda ,  Kazuo Mitsui ,  Yoji Yoshimura

发明人： Seiji Endoh ,  Shotaro Tada ,  Toru Kuga ,  Yasuo Takeda ,  Kazuo Mitsui ,  Yoji Yoshimura

IPC分类号： H01R13/627 ,  H01R4/48

CPC分类号： H01R12/79 ,  H01R13/627 ,  H01R23/66

摘要： A connector adapted to be detachably connected to a flat electric cable having terminal members including contact portions and legs connected to the contact portions which are bent in such a manner that the end portions of the legs are staggered alternately in a zigzag manner forming two lines of legs. The end portions of the legs extend either in the axial or the direction perpendicular to the axial direction of the connector. The legs may be made of equal length before bending and or bent preferably such that the ends of all of the legs flow substantially in the same plane.

摘要翻译： 一种适于可拆卸地连接到具有端子构件的扁平电缆的连接器，该端子构件包括接触部分和连接到接触部分的腿，所述接触部分和腿部以这样的方式弯曲，使得腿部的端部以锯齿形交替地交错形成两条线 腿 腿的端部在垂直于连接器的轴向方向的轴向或方向上延伸。 腿可以在弯曲之前由相同的长度制成并且优选地弯曲，使得所有腿的端部基本上在相同的平面中流动。

公开(公告)号：US07238992B2

公开(公告)日：2007-07-03

申请号：US11034884

申请日：2005-01-14

申请人： Yuri Komori ,  Kazuo Mitsui

发明人： Yuri Komori ,  Kazuo Mitsui

IPC分类号： H01L29/78 ,  G05F1/00 ,  G05F1/62

CPC分类号： H01L27/0623 ,  H01L27/0821 ,  H02M3/1588 ,  Y02B70/1466

摘要： In a semiconductor integrated circuit for a DC—DC converter, an nMOS-type transistor Qn of a CMOS inverter 1c constituting a driver 1 is electrically floated from a substrate 12 through an n-type well region 11. Thus, the nMOS-type transistor Qn is electrically insulated from other transistors such as an npn-type transistor Q1 and an L-pnp-type transistor Q2 constituting a feedback control system 9 through the n-type well region 11. Stable operation is performed with a minute current without producing a malfunction caused by the influence of a parasitic current, even if the drain potential of an nMOS-type transistor is reduced to the ground potential or lower at the time of switching by a driver constituted from a CMOS inverter, to facilitate lower power consumption and higher efficiency, and also to eliminate a constraint on layout design of components.

摘要翻译： 在用于DC-DC转换器的半导体集成电路中，构成驱动器1的CMOS反相器1c的nMOS型晶体管Qn通过n型阱区11从衬底12浮置。 因此，nMOS型晶体管Qn通过n型阱区域11与构成反馈控制系统9的npn型晶体管Q 1和L-pnp型晶体管Q 2等其它晶体管电绝缘。 即使在使用由nMOS型晶体管构成的驱动器切换时，nMOS型晶体管的漏极电位降低到接地电位以下时，也能以微小的电流进行稳定的动作而不产生由寄生电流的影响引起的故障 CMOS逆变器，以便于降低功耗和更高的效率，并且消除对组件布局设计的约束。

公开(公告)号：US5034684A

公开(公告)日：1991-07-23

申请号：US426010

申请日：1989-10-24

申请人： Kazuo Mitsui ,  Hiroshi Suzuki ,  Toshihiro Hosoda ,  Toshihiko Iijima ,  Shinji Niwa ,  Tetsuji Watanabe ,  Hideo Sakagawa ,  Tetsuo Sato

发明人： Kazuo Mitsui ,  Hiroshi Suzuki ,  Toshihiro Hosoda ,  Toshihiko Iijima ,  Shinji Niwa ,  Tetsuji Watanabe ,  Hideo Sakagawa ,  Tetsuo Sato

IPC分类号： G01R31/28

CPC分类号： G01R31/2831

摘要： A probe device having a loader unit and two measuring units is disclosed. Each of the loader and measuring units is an independent unit supported by an independent casing. Each of the loader and measuring units has its exclusive slave CPU and integrated circuit members are under the control of this slave CPU to manage operations of members at the unit. The slave CPUs are connected to a master CPU, which controls the slave CPUs and which is also an independent unit, and they are connected to one another only through the master CPU. Program language is common to the master and slave CPUs and the units can be electrically connected to form an integral control system in which signals are exchanged among the units.

摘要翻译： 公开了一种具有装载单元和两个测量单元的探针装置。 每个装载机和测量单元是由独立的壳体支撑的独立单元。 每个装载机和测量单元都有其独有的从属CPU，集成电路组件由该从CPU控制，以管理设备中的成员的操作。 从CPU连接到主CPU，主CPU控制从站CPU，也是独立单元，它们仅通过主站CPU相互连接。 程序语言对于主从CPU是通用的，并且单元可以被电连接以形成在单元之间交换信号的集成控制系统。

公开(公告)号：US4926421A

公开(公告)日：1990-05-15

申请号：US262938

申请日：1988-10-18

申请人： Minori Kawano ,  Kazuo Mitsui ,  Masaharu Hirooka ,  Yasushi Ozu ,  Nagayasu Harada ,  Nobuhiro Kimura

发明人： Minori Kawano ,  Kazuo Mitsui ,  Masaharu Hirooka ,  Yasushi Ozu ,  Nagayasu Harada ,  Nobuhiro Kimura

IPC分类号： H04W36/00 ,  H04W72/08

CPC分类号： H04W72/085 ,  H04W36/30

摘要： In a mobile radio telephone system having multiple base stations controlled by a single line control unit, all base stations use a single common control channel in addition to their voice channels to communicate with a mobile station. If a calling signal from a mobile station is received by two or more base stations at once on the common control channel, the base station with the highest received signal level is selected. If voice signal quality becomes degraded during a call, the call is handed off to the base station with the highest received signal level.

摘要翻译： 在具有由单线控制单元控制的多个基站的移动无线电话系统中，除了其语音信道之外，所有基站还使用单个公共控制信道来与移动台进行通信。 如果来自移动站的呼叫信号由两个或多个基站在公共控制信道上同时接收，则选择具有最高接收信号电平的基站。 如果在通话期间语音信号质量下降，则呼叫被切换到具有最高接收信号电平的基站。

公开(公告)号：US5333081A

公开(公告)日：1994-07-26

申请号：US952605

申请日：1992-09-28

申请人： Kazuo Mitsui

发明人： Kazuo Mitsui

IPC分类号： G11B5/09 ,  G11B5/02 ,  H03K17/66

CPC分类号： G11B5/022 ,  G11B5/02 ,  H03K17/662

摘要： A magnetic head driving circuit is provided which has first and second transistors having the bases respectively connected to first and second input terminals and the collectors supplied with a power source voltage, third and fourth transistors having the collectors respectively connected to the emitters of the first and second transistors, and a magnetic head and surge absorbing resistor disposed in a parallel connection with each other between the emitters of the first and second transistors. Delay circuits are respectively disposed between the input terminal and the base of the fourth transistor and between the second input terminal and the base of the third transistor. If there has a time delay in inverting action generated between the first and second transistors, the reverse bias voltage acting between the base and emitter of the first and/or second transistor will be impossible to be increased, so that the switching time of the magnetic head current can be shortened. The magnetic recording density can also be improved.

摘要翻译： 提供一种磁头驱动电路，其具有第一和第二晶体管，其基极分别连接到第一和第二输入端子，并且集电极被提供有电源电压，第三和第四晶体管的集电极分别连接到第一和第二输入端的发射极， 第二晶体管，以及在第一和第二晶体管的发射极之间彼此并联连接设置的磁头和浪涌吸收电阻器。 延迟电路分别设置在第四晶体管的输入端和基极之间以及第二输入端和第三晶体管的基极之间。 如果在第一和第二晶体管之间产生的反相动作存在时间延迟，则不可能增加作用在第一和/或第二晶体管的基极和发射极之间的反向偏置电压，从而磁性的切换时间 头电流可以缩短。 也可以提高磁记录密度。

公开(公告)号：US4915649A

公开(公告)日：1990-04-10

申请号：US221913

申请日：1988-07-20

申请人： Hiroyuki Shimazu ,  Kazuo Mitsui

发明人： Hiroyuki Shimazu ,  Kazuo Mitsui

IPC分类号： G03G15/01 ,  F16F15/04 ,  G03G15/09 ,  H01R4/64 ,  H01R13/70 ,  H01R13/703 ,  H01R13/707 ,  H05K7/04 ,  H05K7/14

CPC分类号： H01R13/7032

摘要： A connector comprises a housing provided with a recess (7), a terminal cavity (9) and a gap (10), and a contact piece (2) provided with a base portion (2') and bifurcated free ends (3, 3'). Contact terminals (6, 6') of wires (W, W'), project into the recess through the terminal cavity. The base portion of the contact piece is fitted into the gap, the bifurcated free ends of the contact piece project into the recess, and only one of the bifurcated free ends is normally in contact with one of the contact terminals. Therefore, when an arm of the housing of an other connector is fitted into the recess, the other of the bifurcated free ends is brought into contact with the other of the contact terminals and completes an electrical connection between them.