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公开(公告)号：US09386246B2
公开(公告)日：2016-07-05
申请号：US14076597
申请日：2013-11-11
Applicant: Seiko Instruments Inc.
Inventor： Tsutomu Tomioka , Daisuke Muraoka
CPC classification number: H04N5/3694 , H04N5/3742
Abstract: To provide a small-area photoelectric conversion device without impairing a resolution switching function, signals for controlling output order control switches provided so as to correspond to photoelectric conversion elements are selected by an output order control circuit and a shift register. In this manner, the number of flip-flops forming a shift register is reduced.
Abstract translation: 为了提供小面积光电转换装置而不损害分辨率切换功能，通过输出顺序控制电路和移位寄存器选择用于控制提供以对应于光电转换元件的输出顺序控制开关的信号。 以这种方式，减少了形成移位寄存器的触发器的数量。
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2.发明授权Voltage regulator capable of stabilizing an output voltage even when a power supply fluctuates 有权即使电源波动，也能够稳定输出电压的电压调节器公开(公告)号：US09367074B2
公开(公告)日：2016-06-14
申请号：US14551813
申请日：2014-11-24
Applicant: Seiko Instruments Inc.
Inventor： Tsutomu Tomioka , Masakazu Sugiura
Abstract: Provided is a voltage regulator configured to suppress overshoot and undershoot so as to output a stabilized voltage. The voltage regulator includes: a high pass filter configured to detect a fluctuation in power supply voltage; a high pass filter configured to detect a fluctuation in output voltage; transistors connected in series, which are each configured to cause a current to flow in accordance with an output of corresponding one of the high pass filters; and a clamp circuit configured to clamp a drain voltage of one of the transistors connected in series. The voltage regulator controls a gate voltage of an output transistor based on a drain voltage of a transistor that includes a gate controlled by the drain voltage of the one of the transistors connected in series.
Abstract translation: 提供了一种被配置为抑制过冲和下冲以便输出稳定的电压的电压调节器。 电压调节器包括：高通滤波器，被配置为检测电源电压的波动; 高通滤波器，被配置为检测输出电压的波动; 串联连接的晶体管，其各自被配置为根据相应的一个高通滤波器的输出使电流流动; 以及钳位电路，被配置为钳位串联连接的晶体管之一的漏极电压。 电压调节器基于包括由串联连接的晶体管之一的漏极电压控制的栅极的晶体管的漏极电压来控制输出晶体管的栅极电压。
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公开(公告)号：US09219451B2
公开(公告)日：2015-12-22
申请号：US14189580
申请日：2014-02-25
Applicant: Seiko Instruments Inc.
Inventor： Tsutomu Tomioka
CPC classification number: H03F3/387 , H03F3/45475 , H03F3/45968 , H03F2200/261 , H03F2203/45138
Abstract: Provided is an operational amplifier circuit capable of operating with lower current consumption. An amplifier stage, a FIR filter, and a sample and hold circuit are connected in series, thus enabling reduction of an input offset voltage and amplification of an input signal voltage without using an integral circuit. Current consumption of the operational amplifier circuit is reduced because the integral circuit is not used.
Abstract translation: 提供了能够以较低的电流消耗操作的运算放大器电路。 放大器级，FIR滤波器和采样保持电路串联连接，从而能够在不使用积分电路的情况下降低输入失调电压和放大输入信号电压。 由于不使用积分电路，运算放大器电路的电流消耗减少。
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公开(公告)号：US09172332B2
公开(公告)日：2015-10-27
申请号：US14167104
申请日：2014-01-29
Applicant: Seiko Instruments Inc.
Inventor： Tsutomu Tomioka
CPC classification number: H03F1/26 , G06G7/186 , H03F3/387 , H03F3/45475 , H03F2203/45138 , H03F2203/45356 , H03F2203/45512
Abstract: Provided is an operational amplifier circuit having a high tolerance for clock phase difference fluctuations. An FIR filter is used to add an input signal of the FIR filter to a signal obtained by delaying the input signal of the FIR filter. In this manner, chopper noise can be removed. Thus, the operational amplifier circuit may have a high tolerance for clock phase difference fluctuations regardless of the phase difference between clocks for controlling a chopper circuit and the FIR filter.
Abstract translation: 提供了对时钟相位差波动具有高容差的运算放大器电路。 FIR滤波器用于将FIR滤波器的输入信号添加到通过延迟FIR滤波器的输入信号而获得的信号。 以这种方式，可以去除斩波噪声。 因此，无论用于控制斩波电路和FIR滤波器的时钟之间的相位差如何，运算放大器电路可能具有对时钟相位差波动的高容差。
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公开(公告)号：US09983067B2
公开(公告)日：2018-05-29
申请号：US14692883
申请日：2015-04-22
Applicant: Seiko Instruments Inc.
Inventor： Masakazu Sugiura , Tsutomu Tomioka , Hideyuki Sawai , Atsushi Igarashi , Nao Otsuka , Daisuke Okano
CPC classification number: G01K7/01 , G01K3/005 , H01L27/0255
Abstract: Provided is an overheat detection circuit configured to accurately detect a temperature of a semiconductor device even at high temperature and thus avoid outputting an erroneous detection result. The overheat detection circuit includes: a PN junction element, being a temperature sensitive element; a constant current circuit configured to supply the PN junction element with a bias current; a comparator configured to compare a voltage generated at the PN junction element and a reference voltage; a second PN junction element configured to cause a leakage current to flow through a reference voltage circuit at high temperature; and a third PN junction element configured to bypass a leakage current of the constant current circuit at the high temperature.
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Patent Agency Ranking
公开(公告)号：US09831757B2
公开(公告)日：2017-11-28
申请号：US14568973
申请日：2014-12-12
Applicant: Seiko Instruments Inc.
Inventor： Tsutomu Tomioka , Masakazu Sugiura
CPC classification number: H02M1/088 , G05F1/56 , Y10T307/549
Abstract: Provided is a voltage regulator configured to suppress a variation of an output voltage so as to stably operate even when a power supply voltage varies. The voltage regulator includes a control circuit having an input terminal connected to a drain of an output transistor, and an output terminal connected to an error amplifier circuit. The control circuit is configured to cause a boost current to flow through an error amplifier circuit when the output voltage varies beyond a predetermined value.
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公开(公告)号：US09798341B2
公开(公告)日：2017-10-24
申请号：US14591415
申请日：2015-01-07
Applicant: Seiko Instruments Inc.
Inventor： Tsutomu Tomioka
Abstract: Provided is a voltage regulator including a clamp circuit capable of protecting a gate of an output transistor without limiting a drivability of the output transistor. The voltage regulator includes a level shift circuit having an input terminal connected to the gate of the output transistor and an output terminal connected to an input of the clamp circuit. The clamp circuit is controlled by an output voltage of the level shift circuit.
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公开(公告)号：US09811105B2
公开(公告)日：2017-11-07
申请号：US14596923
申请日：2015-01-14
Applicant: Seiko Instruments Inc.
Inventor： Masakazu Sugiura , Tsutomu Tomioka
CPC classification number: G05F3/16 , G05F3/24 , Y10T307/549
Abstract: To provide a reference voltage circuit capable of outputting a reference voltage excellent in temperature characteristic. A reference voltage circuit includes a first constant current circuit, a first transistor of a first conductivity type which has a source connected to the first constant current circuit and is operated as a first stage source follower, a second constant current circuit, and a second transistor of a second conductivity type which has a gate connected to the source of the first transistor and a source connected to the second constant current circuit and is operated as a second stage source follower. The reference voltage circuit is configured to output a reference voltage from the source of the second transistor.
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公开(公告)号：US09671802B2
公开(公告)日：2017-06-06
申请号：US14968129
申请日：2015-12-14
Applicant: Seiko Instruments Inc.
Inventor： Masakazu Sugiura , Tsutomu Tomioka
CPC classification number: G05F1/565
Abstract: Provided is a voltage regulator capable of applying an optimal overshoot suppression unit depending on states. The voltage regulator includes: an amplifier for controlling an output transistor based on a voltage obtained by amplifying a difference between a divided voltage and a reference voltage; a first overshoot suppression unit for controlling a gate voltage of the output transistor, to thereby suppress overshoot of the output voltage; a second overshoot suppression unit for controlling an operating current of the amplifier, to thereby suppress the overshoot of the output voltage; and a control circuit. The control circuit is configured to turn on the first overshoot suppression unit immediately after the voltage regulator is powered on, and turn off the first overshoot suppression unit under a state in which the output voltage is stable.
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公开(公告)号：US09543905B2
公开(公告)日：2017-01-10
申请号：US14594773
申请日：2015-01-12
Applicant: Seiko Instruments Inc.
Inventor： Tsutomu Tomioka
CPC classification number: H03F1/523 , H03F1/223 , H03F2200/441
Abstract: Provided is an amplifier circuit including an NMOS transistor having a low drain breakdown voltage and an NMOS transistor having a high drain breakdown voltage connected in series thereto, and capable of preventing breakdown of a drain of the NMOS transistor having a low drain breakdown voltage. A clamp circuit configured to limit a drain voltage of the NMOS transistor having a low drain breakdown voltage is connected to the drain thereof.
Abstract translation: 提供了包括具有低漏极击穿电压的NMOS晶体管和具有与其串联连接的高漏极击穿电压的NMOS晶体管的放大器电路，并且能够防止具有低漏极击穿电压的NMOS晶体管的漏极击穿。 配置成限制具有低漏极击穿电压的NMOS晶体管的漏极电压的钳位电路连接到其漏极。
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