公开(公告)号：US20140127868A1

公开(公告)日：2014-05-08

申请号：US14151036

申请日：2014-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

Abstract translation: 提供了一种小型化的晶体管，其产率高。 此外，提供了具有高导通状态特性并且能够进行高速响应和高速操作的半导体器件。 在半导体装置中，依次层叠氧化物半导体层，栅极绝缘层，栅极电极层，绝缘层，导电膜和层间绝缘层。 通过切割导电膜以自对准的方式形成源电极层和漏电极层，从而去除栅极电极层和导电层上的导电膜，并且导电膜被分割。 设置与氧化物半导体层接触并与与源极电极层和漏极电极层接触的区域重叠的电极层。

公开(公告)号：US20140051209A1

公开(公告)日：2014-02-20

申请号：US14062000

申请日：2013-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC: H01L29/66 ,  H01L21/44

CPC classification number: H01L27/1262 ,  H01L21/44 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.

Abstract translation: 描述了一种用于制造半导体器件的方法。 在绝缘膜上形成掩模，并且掩模的尺寸减小。 使用尺寸减小的掩模形成具有突起的绝缘膜，并且使用具有突起的绝缘膜形成沟道长度减小的晶体管。 此外，在制造晶体管时，在与微细突起的顶面重叠的栅极绝缘膜的表面上进行平坦化处理。 因此，晶体管可以高速运转，可提高可靠性。 此外，绝缘膜被加工成具有突起的形状，由此可以以自对准的方式形成源电极和漏电极。

公开(公告)号：US20150093855A1

公开(公告)日：2015-04-02

申请号：US14567235

申请日：2014-12-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Akihiro ISHIZUKA ,  Shinya SASAGAWA

IPC: H01L21/4757 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/47573 ,  H01L21/02554 ,  H01L21/02587 ,  H01L21/02639 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a miniaturized semiconductor device with stable electric characteristics in which a short-channel effect is suppressed. Further, to provide a manufacturing method of the semiconductor device. The semiconductor device (transistor) including a trench formed in an oxide insulating layer, an oxide semiconductor film formed along the trench, a source electrode and a drain electrode which are in contact with the oxide semiconductor film, a gate insulating layer over the oxide semiconductor film, a gate electrode over the gate insulating layer is provided. The lower corner portions of the trench are curved, and the side portions of the trench have side surfaces substantially perpendicular to the top surface of the oxide insulating layer. Further, the width between the upper ends of the trench is greater than or equal to 1 time and less than or equal to 1.5 times the width between the side surfaces of the trench.

Abstract translation: 提供具有稳定电特性的小型化半导体器件，其中抑制短沟道效应。 此外，提供半导体器件的制造方法。 包括形成在氧化物绝缘层中的沟槽，沿着沟槽形成的氧化物半导体膜，与氧化物半导体膜接触的源电极和漏电极的半导体器件（晶体管），氧化物半导体上的栅极绝缘层 提供了栅极绝缘层上的栅电极。 沟槽的下角部分是弯曲的，并且沟槽的侧部具有大致垂直于氧化物绝缘层的顶表面的侧表面。 此外，沟槽的上端之间的宽度大于或等于沟槽的侧表面之间的宽度的1倍且小于或等于1.5倍。

公开(公告)号：US20150084049A1

公开(公告)日：2015-03-26

申请号：US14558989

申请日：2014-12-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akihiro ISHIZUKA ,  Yutaka YONEMITSU ,  Shinya SASAGAWA

IPC: H01L23/535 ,  H01L29/786

CPC classification number: H01L23/535 ,  H01L21/31111 ,  H01L27/1225 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor and having improved electric characteristics. The semiconductor device includes an oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The method includes the steps of forming a first insulating film including gallium oxide over and in contact with the oxide semiconductor film; forming a second insulating film over and in contact with the first insulating film; forming a resist mask over the second insulating film; forming a contact hole by performing dry etching on the first insulating film and the second insulating film; removing the resist mask by ashing using oxygen plasma; and forming a wiring electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode through the contact hole.

Abstract translation: 本发明的目的是提供一种制造包括氧化物半导体并具有改善的电特性的半导体器件的方法。 半导体器件包括氧化物半导体膜，与氧化物半导体膜重叠的栅电极，以及与氧化物半导体膜电连接的源电极和漏电极。 该方法包括以下步骤：在氧化物半导体膜上形成包含氧化镓并与其接触的第一绝缘膜; 在所述第一绝缘膜上形成第二绝缘膜并与所述第一绝缘膜接触; 在所述第二绝缘膜上形成抗蚀剂掩模; 通过对所述第一绝缘膜和所述第二绝缘膜进行干蚀刻来形成接触孔; 使用氧等离子体通过灰化去除抗蚀剂掩模; 以及通过所述接触孔形成电连接到所述栅电极，所述源电极和所述漏电极中的至少一个的布线。

公开(公告)号：US20130092925A1

公开(公告)日：2013-04-18

申请号：US13632635

申请日：2012-10-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

Abstract translation: 提供了一种小型化的晶体管，其产率高。 此外，提供了具有高导通状态特性并且能够进行高速响应和高速操作的半导体器件。 在半导体装置中，依次层叠氧化物半导体层，栅极绝缘层，栅极电极层，绝缘层，导电膜和层间绝缘层。 通过切割导电膜以自对准的方式形成源电极层和漏电极层，从而去除栅极电极层和导电层上的导电膜，并且导电膜被分割。 设置与氧化物半导体层接触并与与源极电极层和漏极电极层接触的区域重叠的电极层。

公开(公告)号：US20150179776A1

公开(公告)日：2015-06-25

申请号：US14629575

申请日：2015-02-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo ISOBE ,  Toshinari SASAKI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02667 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696

Abstract: An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.

Abstract translation: 绝缘层设置有突出的结构体，并且设置与突出结构体接触的氧化物半导体层的沟道形成区域，由此沟道形成区域沿三维方向（垂直于衬底的方向）延伸 ）。 因此，可以使晶体管小型化并且延长晶体管的有效沟道长度。 此外，突出结构体的顶表面和侧表面彼此相交的突出结构体的上端角部弯曲，并且氧化物半导体层形成为包括具有c轴的晶体 垂直于曲面。

公开(公告)号：US20150171195A1

公开(公告)日：2015-06-18

申请号：US14576400

申请日：2014-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo ISOBE ,  Toshinari SASAKI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC: H01L29/66 ,  H01L21/477 ,  H01L29/24 ,  H01L21/02 ,  H01L29/786 ,  H01L29/04

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/477 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/7869

Abstract: A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, the upper end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.

Abstract translation: 公开了一种具有包括氧化物半导体膜的晶体管的半导体器件。 在半导体装置中，沿着形成在绝缘层中的沟槽设置氧化物半导体膜。 沟槽包括具有曲率半径大于或等于20nm且小于或等于60nm的弯曲形状的下端拐角部分和上端拐角部分，并且氧化物半导体膜设置成与 底面，下端角部，上端角部和沟槽的内壁面。 氧化物半导体膜包括至少在上端角部上方具有基本上垂直于表面的c轴的晶体。

公开(公告)号：US20130280867A1

公开(公告)日：2013-10-24

申请号：US13924741

申请日：2013-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC: H01L29/66

CPC classification number: H01L29/6675 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696 ,  H01L33/0058 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

公开(公告)号：US20130095587A1

公开(公告)日：2013-04-18

申请号：US13692310

申请日：2012-12-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC: H01L33/00 ,  H01L29/66

CPC classification number: H01L29/6675 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696 ,  H01L33/0058 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

Abstract translation: 本发明提供了一种制造具有少量漏电流的高可靠性半导体器件的方法。 在制造薄膜晶体管的方法中，使用抗蚀剂掩模进行蚀刻以在薄膜晶体管中形成背沟道部分，去除抗蚀剂掩模，蚀刻一部分后沟道以除去蚀刻残留物等 留在后通道部分，由此可以减少由残渣等引起的泄漏电流。 背沟道部分的蚀刻步骤可以通过使用非偏压的干蚀刻来进行。