利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

265 条记录 (耗时 0.031 秒)

    Multi-cell organic memory element and methods of operating and fabricating
    3.
    发明授权
    Multi-cell organic memory element and methods of operating and fabricating 有权
    多单元有机存储元件及其操作和制造方法

    公开(公告)号：US06900488B1

    公开(公告)日：2005-05-31

    申请号：US10284946

    申请日：2002-10-31

    申请人： Sergey D. Lopatin ,  Mark S. Chang ,  Minh Van Ngo ,  Patrick K. Cheung

    发明人： Sergey D. Lopatin ,  Mark S. Chang ,  Minh Van Ngo ,  Patrick K. Cheung

    IPC分类号： H01L27/28 ,  H01L51/00 ,  H01L51/30 ,  H01L51/40 ,  H01L29/76

    CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0021 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/0077 ,  H01L51/0078

    摘要： The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of the lower electrode. An Inter Layer Dielectric (ILD) is formed above the passive layers and lower electrode, whereby a via or other type relief is created within the ILD and an organic semiconductor material is then utilized to partially fill the via above the passive layer. The portions of the via that are not filled with organic material are filled with dielectric material, thus forming a multi-dimensional memory structure above the passive layer or layers and the lower electrode. One or more top electrodes are then added above the memory structure, whereby distinctive memory cells are created within the organic portions of the memory structure and activated (e.g., read/write) between the top electrodes and bottom electrode, respectively. In this manner, multiple storage cells can be formed within a singular organic structure thereby increasing memory device density and storage.

    摘要翻译： 本发明提供一种多小区有机存储装置，其可以作为具有构造在存储装置内的多个多小区结构的非易失性存储装置来操作。 可以形成下电极，其中在下电极的顶部上形成一个或多个钝化层。 在无源层和下电极之上形成层间电介质（ILD），由此在ILD内产生通孔或其它类型的浮雕，然后利用有机半导体材料部分地填充钝化层以上的通孔。 通孔中没有填充有机材料的部分用电介质材料填充，从而在钝化层或下层电极之上形成多维存储结构。 然后在存储器结构上方添加一个或多个顶部电极，由此在存储器结构的有机部分内分别创建独特的存储单元，并分别在顶部电极和底部电极之间激活（例如，读取/写入）。 以这种方式，可以在单个有机结构内形成多个存储单元，从而增加存储器件密度和存储。

    Silicon containing material for patterning polymeric memory element
    4.
    发明授权
    Silicon containing material for patterning polymeric memory element 有权
    含硅材料用于图案化聚合物记忆元件

    公开(公告)号：US06803267B1

    公开(公告)日：2004-10-12

    申请号：US10614484

    申请日：2003-07-07

    申请人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

    发明人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

    IPC分类号： H01L21336

    CPC分类号： H01L27/28 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0018

    摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.

    摘要翻译： 本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料 上电极通过有机半导体材料和被动材料到下电极。 有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。 此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。 分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。

    Etch-back process for capping a polymer memory device
    8.
    发明授权
    Etch-back process for capping a polymer memory device 有权
    用于封盖聚合物存储器件的蚀刻工艺

    公开(公告)号：US07323418B1

    公开(公告)日：2008-01-29

    申请号：US11102004

    申请日：2005-04-08

    申请人： Minh Van Ngo ,  Angela T. Hui ,  Sergey D. Lopatin

    发明人： Minh Van Ngo ,  Angela T. Hui ,  Sergey D. Lopatin

    IPC分类号： H01L21/302

    CPC分类号： G11C13/0016 ,  G11C13/0014 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/1608 ,  H01L45/1683 ,  H01L51/0591

    摘要： The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides tiny electrical contacts necessary for the proper functioning of polymer memory devices that utilize the vias. In one instance of the present invention, one or more via openings are formed in a dielectric layer to expose an underlying layer. A polymer layer is then formed within the via on the underlying layer with a top electrode material layer deposited over the polymer layer, filling the remaining portion of the via. Excess portions of the top electrode material are then removed by an etching process to form an electrode cap that provides an electrical contact point for the polymer memory element.

    摘要翻译： 本发明利用回蚀工艺来提供用于聚合物存储元件的电极帽。 这允许聚合物存储元件形成在嵌入在衬底上形成的层中的通孔内。 通过利用回蚀工艺，本发明提供了利用通孔的聚合物存储器件的适当功能所需的微小电触点。 在本发明的一个实例中，在电介质层中形成一个或多个通孔以露出下层。 然后在下层上的通孔内形成聚合物层，其中沉积在聚合物层上的顶部电极材料层填充通孔的剩余部分。 然后通过蚀刻工艺去除顶部电极材料的多余部分以形成提供聚合物存储元件的电接触点的电极帽。

    Amorphized barrier layer for integrated circuit interconnects
    9.
    发明授权
    Amorphized barrier layer for integrated circuit interconnects 有权
    用于集成电路互连的非晶化阻挡层

    公开(公告)号：US06348732B1

    公开(公告)日：2002-02-19

    申请号：US09715702

    申请日：2000-11-18

    申请人： Sergey D. Lopatin ,  Minh Van Ngo ,  Minh Quoc Tran

    发明人： Sergey D. Lopatin ,  Minh Van Ngo ,  Minh Quoc Tran

    IPC分类号： H01L2348

    CPC分类号： H01L21/76843 ,  H01L21/76862 ,  H01L21/76873 ,  H01L23/53209 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

    摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 电介质层位于半导体衬底上，其中设有开口。 非晶化的阻挡层对开口进行排列，并且沉积种子层以使非晶化的阻挡层排列。 导体芯填充阻挡层上的开口以形成导体通道。 种子层牢固地结合到非晶化阻挡层并防止沿种子和阻挡层之间的表面的电迁移。