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公开(公告)号：US06920539B2
公开(公告)日：2005-07-19
申请号：US10183234
申请日：2002-06-26
CPC分类号： G06F13/161
摘要： Briefly, in accordance with an embodiment of the invention, a method and system to retrieve information from a memory is provided. The method may include transferring information from the memory in response to at least two synchronous burst read requests using pipelining.
摘要翻译： 简而言之，根据本发明的实施例，提供了一种从存储器检索信息的方法和系统。 该方法可以包括响应于使用流水线化的至少两个同步突发读取请求从存储器传送信息。
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公开(公告)号：US08489780B2
公开(公告)日：2013-07-16
申请号：US11644474
申请日：2006-12-21
CPC分类号： G11C16/30
摘要： Some embodiments of the invention may use a single control line signal as both a wake up signal and as an indicator of a device selection command. In a command-based protocol on a non-volatile memory bus, a host memory controller may assert a signal on a control line to bring all the memory devices on the bus into an operational mode, while concurrently placing a device selection command on the input/output lines. The memory device selected by the selection command may remain operational to perform a sequence of operations as directed by the host controller. The remaining (non-selected) memory devices may return to a sleep mode until a new signal on the control line is received, indicating a new selection command.
摘要翻译： 本发明的一些实施例可以使用单个控制线信号作为唤醒信号和作为设备选择命令的指示符。 在非易失性存储器总线上的基于命令的协议中，主机存储器控制器可以在控制线路上断言信号，以使总线上的所有存储器件进入操作模式，同时在输入端上设置设备选择命令 /输出线。 由选择命令选择的存储器件可以保持运行，以执行由主机控制器指导的操作序列。 剩余的（未选择的）存储器件可以返回睡眠模式，直到接收到控制线上的新信号，指示新的选择命令。
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公开(公告)号：US5485422A
公开(公告)日：1996-01-16
申请号：US252684
申请日：1994-06-02
申请人： Mark E. Bauer , Kevin W. Frary , Sanjay S. Talreja
发明人： Mark E. Bauer , Kevin W. Frary , Sanjay S. Talreja
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632 , G11C2211/5641
摘要： A memory device is disclosed which includes memory cells having m possible states, where m is at least 2. The memory device includes a multiplexed pair of output paths, wherein each output path is coupled to sense the state of a memory cell and includes a read path circuit, a column load circuit, and a comparator. Provided between the pair of output paths is a switching circuit for coupling the comparators to one another in response to a control signal. For single-bit read operations, each output path senses and outputs the data of the associated memory cell, and the control signal is inactive. When the control signal is active, the read path circuit and column load circuit of one of the output paths is disabled and the switching circuit couples the other read path circuit to the second comparator such that the state of the memory cell is sensed by two comparators.
摘要翻译： 公开了一种存储器件，其包括具有m个可能状态的存储器单元，其中m至少为2.存储器件包括多路输出路径对，其中每个输出路径被耦合以感测存储器单元的状态，并且包括读取 路径电路，列负载电路和比较器。 在一对输出路径之间设置有用于响应于控制信号将比较器彼此耦合的开关电路。 对于单位读取操作，每个输出路径检测并输出相关存储单元的数据，并且控制信号无效。 当控制信号有效时，其中一个输出路径的读路径电路和列负载电路被禁止，并且开关电路将另一个读路径电路耦合到第二比较器，使得存储单元的状态由两个比较器 。
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4.发明授权Gate/source disturb protection for sixteen-bit flash EEPROM memory arrays 失效十六位闪存EEPROM存储器阵列的门/源干扰保护
公开(公告)号：US5317535A
公开(公告)日：1994-05-31
申请号：US901110
申请日：1992-06-19
CPC分类号： G11C16/3427 , G11C16/12
摘要： In a flash EEPROM memory array in which a plurality of floating gate field effect transistor memory devices are arranged in rows and columns, in which wordlines are utilized to select rows of such devices and bitlines are utilized to select columns of such devices, in which groups of such devices are arranged in blocks which are independently erasable, and the blocks are divided into sub-blocks for storing lower and upper bytes of words to be stored, apparatus is provided for disabling the wordlines to all high byte sub-blocks when a low byte sub-block is to be programmed, for disabling the wordlines to all low byte sub-blocks when a high byte sub-block is to be programmed, for grounding the sources of all high byte sub-blocks when a low byte sub-block is to be programmed, and for grounding the sources of all low byte sub-blocks when a high byte sub-block is to be programmed.
摘要翻译： 在其中以行和列布置多个浮动栅场效应晶体管存储器件的快闪EEPROM存储器阵列中，其中利用字线来选择这些器件的行和位线来选择这些器件的列，其中组 这些设备被排列成可独立地可擦除的块，并且块被划分成用于存储待存储的字的较低字节和高字节的子块，当低位设置用于禁止字线到所有高字节子块的装置 要编程字节子块，当要编程高字节子块时禁止字线到所有低字节子块，用于在低字节子块时接地所有高字节子块的源 要编程高字节子块时，要对所有低字节子块的源进行接地编程。
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公开(公告)号：US06587373B2
公开(公告)日：2003-07-01
申请号：US10266779
申请日：2002-10-08
申请人： Sanjay S. Talreja
发明人： Sanjay S. Talreja
IPC分类号： G11C1604
CPC分类号： G11C11/5642 , G11C7/1006 , G11C16/08
摘要： A multilevel cell memory may use an architecture in which bits from different words are stored in the same multilevel memory cell. This may improve access time because it is not necessary to sense both cells before the word can be outputted. Therefore, the access time may be improved by removing a serial element from the access chain.
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公开(公告)号：US5742787A
公开(公告)日：1998-04-21
申请号：US419357
申请日：1995-04-10
申请人： Sanjay S. Talreja
发明人： Sanjay S. Talreja
CPC分类号： G11C16/10 , G11C16/102
摘要： A method of quickly aborting an automated program or erase sequence on a nonvolatile memory array in which each operation of the sequence is performed by a write state machine. During each operation of the program or erase sequence, the state of an abort signal is detected to determine whether or not the sequence should be aborted. If the abort signal is in a second state, the sequence continues to the next operation. If the abort signal is in a first state, the write state machine aborts the sequence and the nonvolatile memory array is placed in a read-only mode. The nonvolatile memory array is then available for user access.
摘要翻译： 一种在非易失性存储器阵列中快速地中止自动程序或擦除序列的方法，其中由写入状态机执行序列的每个操作。 在程序或擦除序列的每个操作期间，检测中止信号的状态以确定序列是否应该被中止。 如果中止信号处于第二状态，则该序列继续进行下一个操作。 如果中止信号处于第一状态，则写入状态机中止序列，并且将非易失性存储器阵列置于只读模式。 然后，非易失性存储器阵列可用于用户访问。
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公开(公告)号：US5267196A
公开(公告)日：1993-11-30
申请号：US901279
申请日：1992-06-19
CPC分类号： G11C16/0416 , G11C5/025 , G11C5/063 , G11C8/12
摘要： A nonvolatile memory device residing on a substrate is described. The memory device includes a first block and a second block. The first block includes a first sub-block comprising a first memory cell, a first bit line coupled to a drain of the first memory cell, and a first source line coupled to a source of the first memory cell. The first block also includes a second sub-block which includes a second memory cell, a second bit line coupled to a drain of the second memory cell, and a second source line coupled to a source of the second memory cell. The second block comprises a third sub-block comprising a third memory cell, a third bit line coupled to a drain of the third memory cell, and a third source line coupled to a source of the third memory cell. The second block also includes a fourth sub-block which includes a fourth memory cell, a fourth bit line coupled to a drain of the fourth memory cell, and a fourth source line coupled to a source of the fourth memory cell. The first sub-block of the first block and the third sub-block of the second block are grouped together on the substrate to form a first data bit group corresponding to a first data pin of the memory device such that the distances of the first and third memory cells of the first data bit group to a first sensing circuit are substantially minimized and are substantially equal. The second sub-block of the first block and the fourth sub-block of the second block are grouped together on the substrate to form a second data bit group corresponding to a second data pin of the memory device such that the distances of the second and fourth memory cells of the second data bit group to a second sensing circuit are substantially minimized and are substantially equal.
摘要翻译： 描述驻留在基板上的非易失性存储器件。 存储器件包括第一块和第二块。 第一块包括第一子块，其包括第一存储器单元，耦合到第一存储器单元的漏极的第一位线和耦合到第一存储器单元的源极的第一源极线。 第一块还包括第二子块，其包括第二存储器单元，耦合到第二存储单元的漏极的第二位线和耦合到第二存储器单元的源极的第二源极线。 第二块包括第三子块，其包括第三存储器单元，耦合到第三存储器单元的漏极的第三位线以及耦合到第三存储器单元的源极的第三源极线。 第二块还包括第四子块，其包括第四存储单元，耦合到第四存储单元的漏极的第四位线和耦合到第四存储单元的源极的第四源极线。 第一块的第一子块和第二块的第三子块在衬底上分组在一起以形成与存储器件的第一数据引脚相对应的第一数据位组，使得第一和第 第一数据位组的第三存储单元基本上最小化并且基本相等。 第一块的第二子块和第二块的第四子块在衬底上分组在一起以形成与存储器件的第二数据管脚相对应的第二数据位组，使得第二和 第二数据位组的第四存储单元基本上被最小化并且基本相等。
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公开(公告)号：US06931498B2
公开(公告)日：2005-08-16
申请号：US09827134
申请日：2001-04-03
CPC分类号： G11C16/26 , G11C16/10 , G11C2216/22
摘要： A single status register, capable of providing status for simultaneous read-while-write operation on a flash memory array is described. The status of the memory array is reported to the user based on two partitions. A microcontroller is used to traffic the status register to memory array communication.
摘要翻译： 描述了能够提供闪速存储器阵列上的同时读写同时操作的状态的单个状态寄存器。 基于两个分区向用户报告内存阵列的状态。 微控制器用于将状态寄存器传送到存储器阵列通信。
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公开(公告)号：US5539690A
公开(公告)日：1996-07-23
申请号：US252747
申请日：1994-06-02
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634
摘要： Schemes for verifying the successful programming of a memory cell having more than two possible states are disclosed. Each program verify reference flash cell is set to have a V.sub.t that defines a boundary of a possible state for the selected flash cell. For a first embodiment, program verify reference flash cells are used in the place of read reference cells to perform a binary search read operation similar to a standard read operation for the memory device architecture. The data sensed by the write verify operation is compared to expected data. For a second embodiment, a single program verify reference flash cell is used to define a threshold voltage beyond which the floating gate of the selected flash cell must be programmed to pass the write verify operation. Thus, for the second embodiment, the program verify reference flash cell is used to verify the analog V.sub.t voltage level of the selected flash cell, rather than to determine the data of the selected flash cell, as is done for the first embodiment.
摘要翻译： 公开了用于验证具有两个以上可能状态的存储单元的成功编程的方案。 每个程序验证参考闪存单元被设置为具有定义所选闪存单元的可能状态的边界的Vt。 对于第一实施例，使用程序验证参考闪存单元来代替读取参考单元来执行类似于用于存储器件架构的标准读取操作的二进制搜索读取操作。 将通过写入验证操作感测的数据与预期数据进行比较。 对于第二实施例，使用单个程序验证参考闪存单元来定义阈值电压，超过该阈值电压的所选闪存单元的浮置栅极必须被编程以通过写入验证操作。 因此，对于第二实施例，程序验证参考闪存单元用于验证所选择的闪存单元的模拟Vt电压电平，而不是确定所选择的闪存单元的数据，如第一实施例所做的那样。
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10.发明授权User selectable word/byte input architecture for flash EEPROM memory write and erase operations 失效用户可选择的字/字节输入架构，用于闪存EEPROM存储器的写入和擦除操作
公开(公告)号：US5379413A
公开(公告)日：1995-01-03
申请号：US901396
申请日：1992-06-19
CPC分类号： G11C29/38 , G11C7/1006
摘要： A circuit for accessing data which may be stored in a flash EEPROM memory array in sixteen bit quantities has apparatus for writing data to the array in eight bit quantities which quantities may be either the lower or upper byte of a word and appear at identical input terminals, apparatus for writing data to the array in sixteen bit quantities, apparatus for reading data from the array to identical output terminals in eight bit quantities which quantities may be either the lower or upper byte of a word, and apparatus for reading data from the array in sixteen bit quantities. The circuit also has apparatus for reading data from the array in eight and sixteen bit quantities during periods in which an erase operation conducted on sixteen bits is suspended.
摘要翻译： 用于以十六位数存储在快闪EEPROM存储器阵列中的数据访问电路具有用于以八位数将数据写入阵列的装置，该数量可以是字的较低或高字节，并出现在相同的输入端 用于以十六位数据将数据写入阵列的装置，用于以八位数量从阵列读取数据到相同输出端的装置，该数量可以是字的较低或高字节，以及用于从阵列读取数据的装置 十六位数。 电路还具有用于在暂停执行16位擦除操作的周期期间以8位和16位数据从阵列读取数据的装置。
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