公开(公告)号：US08461548B2

公开(公告)日：2013-06-11

申请号：US13377253

申请日：2010-04-27

申请人： Dan Nicolaescu ,  Shigeki Sakai ,  Junzo Ishikawa ,  Yasuhito Gotoh

发明人： Dan Nicolaescu ,  Shigeki Sakai ,  Junzo Ishikawa ,  Yasuhito Gotoh

IPC分类号： H01J3/26

CPC分类号： H01J37/3171 ,  H01J2237/004 ,  H01J2237/0041 ,  H01J2237/0048 ,  H01J2237/06341 ,  H01J2237/083 ,  H01J2237/1538 ,  H01J2237/24535 ,  H01J2237/24542

摘要： To improve an efficiency of utilizing electrons and efficiently suppress an ion beam spread by a space charge effect while eliminating a need for a special magnetic pole structure by effectively using a space in the vicinity of a magnet, there are provided an ion source, a collimating magnet and a plurality of electron sources, wherein the electron sources are arranged in a magnetic field gradient region formed on an ion beam upstream side or ion beam downstream side of the collimating magnet and arranged outside a region passed by the ion beam, and an irradiation direction of the electrons is directed to supply the electrons to the magnetic field gradient region.

摘要翻译： 为了提高利用电子的效率，有效地抑制通过空间电荷效应扩散的离子束，同时通过有效地利用磁体附近的空间来消除对专用磁极结构的需要，提供离子源，准直 磁体和多个电子源，其中电子源被布置在形成在准直磁体的离子束上游侧或离子束下游侧的磁场梯度区域中，并且布置在通过离子束的区域的外侧， 电子的方向被引导以将电子提供给磁场梯度区域。

公开(公告)号：US08159873B2

公开(公告)日：2012-04-17

申请号：US12513750

申请日：2007-10-29

申请人： Mitsue Takahashi ,  Shigeki Sakai

发明人： Mitsue Takahashi ,  Shigeki Sakai

IPC分类号： G11C11/34

CPC分类号： H03K19/0185 ,  G11C11/22 ,  G11C11/223 ,  G11C14/00 ,  H01L21/28291 ,  H01L27/105 ,  H01L27/11585 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/78391

摘要： There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and has a function of generating an electric potential of a magnitude capable of performing nonvolatile memory writing into a nonvolatile memory circuit based on an electric potential input to the input terminal and outputting the electric potential of the magnitude to the output terminal, and the nonvolatile memory circuit has a nonvolatile memory function and an input terminal of the nonvolatile memory circuit is connected to the output of the state detection enhancement circuit. The state detection enhancement circuit is a positive or negative logical state detection enhancement circuit which includes a control signal terminal and a switch circuit which is turned on or off by a control signal applied to the control signal terminal, and has a function of either applying an output potential of the same logical state as or an inverse logical state of an input potential applied to the input terminal to the output terminal or completely breaking off a correlation between the input potential and the output potential when the switch circuit is in an OFF state, and has a function of applying an output potential which has the same logical state as or an inverse logical state of the input potential and has a larger highest-lowest potential range including a possible highest-lowest potential range of the input potential to the output terminal when the switch is in an ON state.

摘要翻译： 提供了一种包括状态检测增强电路的半导体集成电路，其包括输入端子和输出端子，并且具有基于电位产生能够进行非易失性存储器写入非易失性存储器电路的幅度的电位的功能 输入到输入端子并将大小的电位输出到输出端子，非易失性存储器电路具有非易失性存储功能，并且非易失性存储器电路的输入端子连接到状态检测增强电路的输出端。 状态检测增强电路是正或负逻辑状态检测增强电路，其包括控制信号端子和通过施加到控制信号端子的控制信号而导通或截止的开关电路，并且具有应用 与输入端子施加到输出端子的输入电位相同的逻辑状态的输出电位或反逻辑状态，或者当开关电路处于OFF状态时完全中断输入电位与输出电位之间的相关性， 并且具有施加与输入电位具有相同逻辑状态或相反逻辑状态的输出电位的功能，并且具有包括输入电位的可能最高最低电位范围的较大最高 - 最低电位范围到输出端 当开关处于ON状态时。

公开(公告)号：US06898105B2

公开(公告)日：2005-05-24

申请号：US10453441

申请日：2003-06-03

申请人： Shigeki Sakai ,  Kazuo Sakamaki

发明人： Shigeki Sakai ,  Kazuo Sakamaki

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  G11C11/24

CPC分类号： G11C11/22

摘要： A ferroelectric non-volatile memory device that allows the coupling ratio to be increased and the effect of voltage distribution to the ferroelectric capacitor to be improved without increasing the area of the gate electrode of a detection MIS field effect transistor is provided. In a memory cell structure, a semiconductor including regions for a source, a channel, and a drain, a gate insulator on the channel region, a floating gate conductor, a ferroelectrics, and an upper electrode conductor are layered in this order. The structure includes a paraelectric capacitor having one end connected to the floating gate conductor and the other end connected to the source region.

摘要翻译： 提供了一种允许提高耦合比并且不增加检测MIS场效应晶体管的栅电极的面积来提高对铁电电容器的电压分布的影响的铁电非易失性存储器件。 在存储单元结构中，依次层叠包括源极，沟道和漏极的区域，沟道区上的栅极绝缘体，浮置栅极导体，铁电体和上部电极导体的半导体。 该结构包括一个直流电容器，其一端连接到浮动栅极导体，另一端连接到源极区域。

公开(公告)号：US06339699B1

公开(公告)日：2002-01-15

申请号：US09153897

申请日：1998-09-16

申请人： Hiroki Hirai ,  Yuichiro Tsutsumi ,  Masashi Sugimoto ,  Tetsuji Tanaka ,  Yasuhiro Hiura ,  Shigeki Sakai ,  Yoshito Sakai

发明人： Hiroki Hirai ,  Yuichiro Tsutsumi ,  Masashi Sugimoto ,  Tetsuji Tanaka ,  Yasuhiro Hiura ,  Shigeki Sakai ,  Yoshito Sakai

IPC分类号： H04B138

CPC分类号： B60R11/0241 ,  B60R2011/0075 ,  H04M1/04

摘要： A phone holder for holding a mobile phone in a connected state with a holder connector. The phone holder has a fixed casing and a movable casing. The movable casing is mounted with the holder connector and formed with a hollow portion therein. The movable casing is mounted on the fixed casing and is settable between a housed position and a detachable position. When set at the detachable position, the hollow portion of the movable casing is accessible to enable insertion of the mobile phone in the movable casing in the connecting direction with the holder connector.

摘要翻译： 一种手持机，用于将手机与连接器连接在一起连接状态。 电话机支架具有固定外壳和可移动外壳。 可动壳体安装有保持器连接器并在其中形成有中空部分。 可动壳体安装在固定壳体上，并可在容纳位置和可拆卸位置之间安装。 当设置在可拆卸位置时，可移动壳体的中空部分是可接近的，以便能够在与保持器连接器的连接方向上将移动电话插入可移动壳体中。

公开(公告)号：US20120085918A1

公开(公告)日：2012-04-12

申请号：US13377253

申请日：2010-04-27

申请人： Dan Nicolaescu ,  Shigeki Sakai ,  Junzo Ishikawa ,  Yasuhito Gotoh

发明人： Dan Nicolaescu ,  Shigeki Sakai ,  Junzo Ishikawa ,  Yasuhito Gotoh

IPC分类号： H01J3/26 ,  H01J3/20

CPC分类号： H01J37/3171 ,  H01J2237/004 ,  H01J2237/0041 ,  H01J2237/0048 ,  H01J2237/06341 ,  H01J2237/083 ,  H01J2237/1538 ,  H01J2237/24535 ,  H01J2237/24542

摘要： To improve an efficiency of utilizing electrons and efficiently suppress an ion beam spread by a space charge effect while eliminating a need for a special magnetic pole structure by effectively using a space in the vicinity of a magnet, there are provided an ion source, a collimating magnet and a plurality of electron sources, wherein the electron sources are arranged in a magnetic field gradient region formed on an ion beam upstream side or ion beam downstream side of the collimating magnet and arranged outside a region passed by the ion beam, and an irradiation direction of the electrons is directed to supply the electrons to the magnetic field gradient region.

摘要翻译： 为了提高利用电子的效率，有效地抑制通过空间电荷效应扩散的离子束，同时通过有效地利用磁体附近的空间来消除对特殊磁极结构的需要，提供离子源，准直 磁体和多个电子源，其中电子源被布置在形成在准直磁体的离子束上游侧或离子束下游侧的磁场梯度区域中，并且布置在通过离子束的区域的外侧， 电子的方向被引导以将电子提供给磁场梯度区域。

公开(公告)号：US20100057839A1

公开(公告)日：2010-03-04

申请号：US12318686

申请日：2009-01-06

申请人： Shigeki Sakai ,  Kazuhiro Ando

发明人： Shigeki Sakai ,  Kazuhiro Ando

IPC分类号： G06F15/16

CPC分类号： G06F8/65

摘要： In a design-system distributing method, when a server side design system is updated, a server compares an updated server side design system and a client update state data, and the server distributes an update assisting system, an update indication data and a difference data to a client system based on the comparing result. The client system stores the update assisting system, the update indication data and the difference data, and the client system starts the stored update assisting system such that an update notice is outputted to a user of the client system to urge update of the client side design system each time a preset condition is satisfied until an update command of the client side design system is supplied to the client system. The client system updates the client side design system based on the stored update indication data and the stored difference data in response to the update command. The client system generates and transmits the client update state data to the server to indicate an update state of the client side design system for this time, and the server updates the client update state data based on the client update state data received from the client system.

摘要翻译： 在设计系统分配方法中，当更新服务器侧设计系统时，服务器将更新的服务器侧设计系统与客户端更新状态数据进行比较，并且服务器分发更新辅助系统，更新指示数据和差异数据 基于比较结果的客户端系统。 客户端系统存储更新辅助系统，更新指示数据和差异数据，并且客户端系统启动存储的更新辅助系统，使得更新通知被输出到客户端系统的用户以促使更新客户端设计 系统，每次满足预设条件，直到客户机侧设计系统的更新命令被提供给客户端系统。 响应于更新命令，客户端系统基于存储的更新指示数据和存储的差分数据更新客户端设计系统。 客户端系统生成并发送客户端更新状态数据到服务器，以指示此时客户端设计系统的更新状态，并且服务器基于从客户端系统接收到的客户端更新状态数据来更新客户端更新状态数据 。

公开(公告)号：US07226795B2

公开(公告)日：2007-06-05

申请号：US10525045

申请日：2003-08-19

申请人： Shigeki Sakai

发明人： Shigeki Sakai

IPC分类号： H01L21/00

CPC分类号： H01L21/02181 ,  C23C16/40 ,  H01L21/02178 ,  H01L21/02194 ,  H01L21/28291 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31683 ,  H01L29/516 ,  H01L29/78391

摘要： The MFIS transistors heretofore have a problem that after data writing, the data disappear in terms of memory transistor operation in about one day at most. This is mainly because the buffer layer and the ferroelectric have a high leakage current and, hence, charge is accumulated around the interface between the ferroelectric and the buffer layer so as to shield the electric polarization memorized by the ferroelectric, making it impossible for the electric polarization of the ferroelectric to control electrical conduction between the source and the drain in the transistor. In the present invention, by constituting an insulator buffer layer 2 of HfO2+u or Hf1−xAl2xO2+x+y, the leakage current flowing through each of the insulator buffer layer 2 and a ferroelectric 3 can be reduced and a memory transistor having a truly sufficient long data holding time is realized.

摘要翻译： 迄今为止，MFIS晶体管存在数据写入之后，在大约一天内存储晶体管操作的数据消失。 这主要是因为缓冲层和铁电体具有高的漏电流，因此电荷积聚在铁电体和缓冲层之间的界面周围，以屏蔽由铁电体存储的电极化，使得电气 铁电体的极化以控制晶体管中的源极和漏极之间的导电。 在本发明中，通过构成HfO 2 + u或Hf 1-x Al 2 O 2 O 2的绝缘体缓冲层2 + x + y ，可以减少流过绝缘体缓冲层2和铁电体3中的每一个的漏电流，并且实现具有真正足够长的数据保持时间的存储晶体管。

公开(公告)号：US20060246211A1

公开(公告)日：2006-11-02

申请号：US10533810

申请日：2003-11-07

申请人： Shigeki Sakai

发明人： Shigeki Sakai

IPC分类号： C23C16/52 ,  H01L21/66 ,  C23C16/00

CPC分类号： C23C14/28 ,  C23C14/542

摘要： A method of forming film on a substrate, in which in a preliminary step information on film thickness deposited on a test substrate prepared for use in collecting information over a fixed irradiation time is obtained in advance while shining a laser beam on a target, there being a fixed positional relationship between spatial positions of the test substrate and an incidence point of the laser beam on the target, or while shining the laser beam on the target while rotating the test substrate. In a main step, a deposition time at each relative positional relationship is adjusted based on film-thickness distribution information obtained in the preliminary step while spatially moving or rotating the substrate or substrate holder about a specific central axis of rotation relative to the incidence point of the laser beam to the target, or while performing both the relative rotation and relative movement.

公开(公告)号：US06753702B2

公开(公告)日：2004-06-22

申请号：US10230197

申请日：2002-08-29

申请人： Masaharu Mizuno ,  Shigeki Sakai ,  Naotaka Maeda

发明人： Masaharu Mizuno ,  Shigeki Sakai ,  Naotaka Maeda

IPC分类号： H03K1900

CPC分类号： H03K19/1737 ,  G06F1/06 ,  G06F1/10 ,  G06F17/5068 ,  H03K19/1735

摘要： The master slice type semiconductor integrated circuit includes sequential circuit cells (2) and combinational circuit cells (3), which are alternately arranged in an inner core area on a semiconductor chip (1), and a plurality of selective driving elements (MC101 to MC108, MC201 to MC216 and MC301 to MC316), which are connected in a shape of a tree, for selectively distributing a poliphase clock signal for each division area formed by uniformly dividing the inner core area. The plurality of selective driving elements are placed and connected on the semiconductor chip such that load and wiring length between the sequential circuit cells within the respective division areas and input terminals to which the poliphase clock signal is inputted are equal. Due to this configuration, it is possible to cope with a poliphase clock, and also possible to reduce a clock skew between circuits, and further possible to provide a master slice type semiconductor integrated circuit in which an electric power consumption can be reduced.

摘要翻译： 主片式半导体集成电路包括交替布置在半导体芯片（1）上的内核区域中的顺序电路单元（2）和组合电路单元（3），以及多个选择驱动元件（MC101至MC108 ，MC201〜MC216以及MC301〜MC316），其以树形连接，用于选择性地分配由均匀分割内芯区域形成的各分割区域的波形时钟信号。 多个选择性驱动元件被放置并连接在半导体芯片上，使得相应的划分区域内的顺序电路单元和输入有相位时钟信号的输入端之间的负载和布线长度相等。 由于这种结构，可以应付脉冲时钟，也可以减少电路之间的时钟偏移，并且还可以提供能够降低电力消耗的主分片式半导体集成电路。

公开(公告)号：US06651582B2

公开(公告)日：2003-11-25

申请号：US09987112

申请日：2001-11-13

申请人： Shigeki Sakai ,  Tadashi Ikejiri

发明人： Shigeki Sakai ,  Tadashi Ikejiri

IPC分类号： C23C1600

CPC分类号： H01J37/026 ,  H01J2237/004 ,  H01J2237/31701 ,  H01L21/2236

摘要： When ion beam 14 is irradiated onto a substrate 2 to conduct processing such as ion injection, plasma 30 emitted from a plasma generating device 20 is supplied to a portion close to the substrate 2 to suppress electric charging on a substrate surface caused by ion beam irradiation. A ratio of IE/IB is kept at a value not lower than 1.8, a ratio of II /IE is kept at a value not lower than 0.07 and not higher than 0.7, wherein IB is an electric current of the ion beam 14 irradiated onto the substrate 2, II is an ion current expressing a quantity of ions in the plasma 30 emitted from the plasma generating device 20, and IE is an electron current expressing a quantity of electrons in the plasma 30.