公开(公告)号：US4717682A

公开(公告)日：1988-01-05

申请号：US830928

申请日：1986-02-19

申请人： Shin-ichi Taka ,  Jiro Ohshima ,  Masahiro Abe ,  Masaharu Aoyama

发明人： Shin-ichi Taka ,  Jiro Ohshima ,  Masahiro Abe ,  Masaharu Aoyama

IPC分类号： H01L21/76 ,  H01L21/265 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/283

CPC分类号： H01L21/743

摘要： A method of manufacturing a semiconductor device, comprising the steps of sequentially forming a buried region and an epitaxial layer on a major surface of a semiconductor substrate, forming a conductive layer along an annular trench extending to the buried region, filling the annular trench with an insulating material and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench. In this method, the step of forming the conductive layer along the annular trench is carried out by the steps of forming an annular trench extending through said buried region, and depositing a conductive layer on only a side wall surface of said annular trench.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底的主表面上依次形成掩埋区域和外延层，沿着延伸到掩埋区域的环形沟槽形成导电层，用环形沟槽填充 绝缘材料，并在由所述掩埋区域围绕的所述外延层中形成功能元件，并在所述环形沟槽内形成所述绝缘材料。 在该方法中，沿着环形沟槽形成导电层的步骤是通过形成延伸穿过所述掩埋区域的环形沟槽以及仅在所述环形沟槽的侧壁表面上沉积导电层的步骤来执行的。

公开(公告)号：US4766086A

公开(公告)日：1988-08-23

申请号：US20758

申请日：1987-03-02

申请人： Jiro Ohshima ,  Shin-ichi Taka ,  Toshiyo Ito ,  Masaharu Aoyama

发明人： Jiro Ohshima ,  Shin-ichi Taka ,  Toshiyo Ito ,  Masaharu Aoyama

IPC分类号： H01L29/73 ,  H01L21/316 ,  H01L21/322 ,  H01L21/331 ,  H01L21/761 ,  H01L29/732 ,  H01L21/265 ,  H01L21/225

CPC分类号： H01L21/3221 ,  H01L21/761 ,  Y10S148/024

摘要： In a method of manufacturing a semiconductor device according to the present invention, a given position of a thermal oxide film formed on a monocrystalline silicon layer is opened to expose a surface of the monocrystalline silicon layer to serve as a getter site, a polycrystalline silicon layer is deposited on the thermal oxide film and the surface of the monocrystalline silicon layer, and the polycrystalline silicon layer is oxidized to convert the surface of the monocrystalline silicon layer directly contacting the polycrystalline silicon layer into an oxide film by thermal oxidation. That is, the position of interface between the oxide film and the monocrystalline silicon layer is shifted into the original monocrystalline silicon layer. During thermal oxidation of the polycrystalline silicon layer, a plurality of crystal defects to serve as getter sites are generated deeper than those generated by a conventional implagetter method in the monocrystalline silicon layer. In addition, the crystal defects generated in the manner described above do not extend to the surrounding region by subsequent annealing so that a region of the crystal defects is limited.

摘要翻译： 在根据本发明的半导体器件的制造方法中，形成在单晶硅层上的热氧化膜的给定位置被打开以暴露单晶硅层的表面以用作吸气部位，多晶硅层 沉积在热氧化膜和单晶硅层的表面上，并且多晶硅层被氧化，以通过热氧化将直接与多晶硅层接触的单晶硅层的表面转化为氧化膜。 也就是说，氧化膜和单晶硅层之间的界面的位置被转移到原始的单晶硅层中。 在多晶硅层的热氧化过程中，产生比用于单晶硅层中常规的投影仪方法产生的多个晶体缺陷作为吸气位置。 此外，以上述方式产生的晶体缺陷通过随后的退火不会延伸到周围区域，使得晶体缺陷的区域受到限制。

公开(公告)号：US4975381A

公开(公告)日：1990-12-04

申请号：US492488

申请日：1990-03-12

申请人： Shin-ichi Taka ,  Jiro Ohshima

发明人： Shin-ichi Taka ,  Jiro Ohshima

IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L21/60 ,  H01L29/732

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L29/66272 ,  Y10S148/011 ,  Y10S148/124

摘要： This invention discloses a method of manufacturing an SST bipolar transistor, and the manufacturing method is capable of defining the size of a base region of the SST bipolar transistor. An insulating film and a spacer film serving as a spacer are sequentially formed in a bipolar transistor forming region on the main surface of a semiconductor substrate. Thereafter, the spacer film is patterned into a spacer film pattern for defining the size of the base region. A second insulating film, a base electrode pattern and a third insulating film are sequentially formed on the spacer film pattern. A first opening which reaches the spacer film pattern through the second insulating film, the base electrode pattern and the third insulating film is formed. The spacer film pattern is etched from the first opening to form a second opening having a diameter larger than that of the first opening. The insulating film exposed in the second opening is etched. The size of the base region on the major surface of the semiconductor substrate is defined by the size of the second opening.

摘要翻译： 本发明公开了一种制造SST双极型晶体管的方法，该制造方法能够限定SST双极型晶体管的基极区域的尺寸。 在半导体基板的主表面上的双极晶体管形成区域中依次形成用作间隔物的绝缘膜和间隔膜。 此后，间隔膜被图案化成用于限定基部区域的尺寸的间隔膜图案。 在间隔膜图案上依次形成第二绝缘膜，基极图案和第三绝缘膜。 形成通过第二绝缘膜到达间隔膜图案的第一开口，基极图案和第三绝缘膜。 从第一开口蚀刻间隔膜图案以形成直径大于第一开口直径的第二开口。 在第二开口中暴露的绝缘膜被蚀刻。 半导体基板的主表面上的基极区域的尺寸由第二开口的尺寸限定。

公开(公告)号：US4853342A

公开(公告)日：1989-08-01

申请号：US300224

申请日：1989-01-24

申请人： Shin-ichi Taka ,  Jiro Ohshima

发明人： Shin-ichi Taka ,  Jiro Ohshima

IPC分类号： H01L29/73 ,  H01L21/20 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78

CPC分类号： H01L29/66287 ,  H01L21/2022 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1087 ,  H01L29/66242 ,  H01L29/66651 ,  H01L29/732 ,  Y10S148/01 ,  Y10S148/011

摘要： A transistor is formed according to the solid phase epitaxial growth which is one of the semiconductor integrated circuit device manufacturing techniques. A low-concentration impurity region is formed by selective solid phase epitaxial growth instead of using an epitaxial substrate. The solid phase epitaxial growth is performed twice, when a collector region is formed and when a base region is formed. The depth of collector and base regions are determined by the thickness of the solid phase growth layers, respectively.

摘要翻译： 根据作为半导体集成电路器件制造技术之一的固相外延生长形成晶体管。 通过选择性固相外延生长而不是使用外延衬底来形成低浓度杂质区。 当形成集电极区域和形成基极区域时，进行固相外延生长两次。 集电极和基极区域的深度分别由固相生长层的厚度决定。

公开(公告)号：US5102826A

公开(公告)日：1992-04-07

申请号：US610216

申请日：1990-11-09

申请人： Jiro Ohshima ,  Shin-ichi Taka ,  Toshiyo Motozima ,  Hiroshi Naruse

发明人： Jiro Ohshima ,  Shin-ichi Taka ,  Toshiyo Motozima ,  Hiroshi Naruse

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/285

CPC分类号： H01L21/26506 ,  H01L21/28518 ,  Y10S148/106

摘要： According to the method of manufacturing a semiconductor device of the present invention, an insulation film is formed on a silicon substrate, and a resist film having a predetermined pattern is formed on the insulation film, followed by forming an opening on the insulation film with the resist film performing as a mask. Then, an impurity having conductivity are implanted into said silicon substrate with the resist film performing as a mask and silicon ions are implanted into the silicon substrate with the resist film performing as a mask. After that, the resist film is removed. Further, a refractory metal film which covers at least the opening is formed. Moveover, a diffusion layer which causes electrical activation of the impurity having conductivity is formed by annealing, followed by formation a silicide layer at where the surfaces of the silicon substrate and the metal film meet.

摘要翻译： 根据本发明的半导体器件的制造方法，在硅衬底上形成绝缘膜，在绝缘膜上形成具有预定图案的抗蚀剂膜，然后在绝缘膜上形成开口 作为掩模的抗蚀膜。 然后，将具有导电性的杂质注入到所述硅衬底中，并以抗蚀剂膜作为掩模将硅离子注入到硅衬底中，并将硅离子注入到硅衬底中。 之后，除去抗蚀剂膜。 此外，形成至少覆盖开口的难熔金属膜。 通过退火形成引起具有导电性的杂质的电活化的扩散层，随后在硅衬底和金属膜的表面相遇处形成硅化物层。

公开(公告)号：US4871685A

公开(公告)日：1989-10-03

申请号：US230823

申请日：1988-08-11

申请人： Shin-ichi Taka ,  Jiro Ohshima

发明人： Shin-ichi Taka ,  Jiro Ohshima

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L21/763 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L21/763 ,  Y10S148/01 ,  Y10S148/011

摘要： A metal layer is formed by selective CVD method on an emitter region formed by using a field oxide film as a mask. Opening for ion-implanting an impurity for forming external base region is formed in the field oxide film by utilizing the metal layer and a metal layer creep up a bird's beak of the field oxide film as masks. An impurity is doped in a semiconductor substrate through the opening formed in the field oxide film to form external base region. The distance between the emitter region and external base region is controlled by a length of the metal layer creep up the bird's beak.

摘要翻译： 通过选择性CVD法在通过使用场氧化膜作为掩模形成的发射极区域上形成金属层。 通过利用金属层在场氧化膜中形成用于离子注入用于形成外部基极区域的杂质的开口，并且金属层将场氧化膜的鸟喙蠕变成掩模。 通过形成在场氧化膜中的开口在半导体衬底中掺杂杂质以形成外部基极区。 发射极区域和外部基极区域之间的距离由金属层的长度在鸟的喙上蠕动控制。

公开(公告)号：US5365090A

公开(公告)日：1994-11-15

申请号：US45707

申请日：1993-04-14

申请人： Shin-ichi Taka ,  Kouji Kimura ,  Hiroshi Naruse ,  Kuniaki Kumamaru

发明人： Shin-ichi Taka ,  Kouji Kimura ,  Hiroshi Naruse ,  Kuniaki Kumamaru

IPC分类号： H01L29/165 ,  H01L21/331 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01L29/72

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： The specification discloses a hetero bipolar transistor which comprises a semiconductor substrate, a first silicon layer serving as a collector, a first silicon-germanium layer serving as a base, a second silicon layer serving as a collector, and a second silicon-germanium layer. A side wall of the second silicon-germanium layer is in contact with side walls of the first silicon layer, the first silicon-germanium layer and the second silicon layer. The second silicon-germanium layer is disposed to surround the first silicon layer, the first silicon-germanium layer, and the second silicon layer, and has an energy band gap substantially the same as that of the first silicon-germanium layer.

摘要翻译： 该说明书公开了一种异质双极晶体管，其包括半导体衬底，用作集电极的第一硅层，用作基极的第一硅 - 锗层，用作集电极的第二硅层和第二硅 - 锗层。 第二硅 - 锗层的侧壁与第一硅层，第一硅 - 锗层和第二硅层的侧壁接触。 第二硅锗层被设置为围绕第一硅层，第一硅 - 锗层和第二硅层，并且具有与第一硅 - 锗层基本相同的能带隙。

公开(公告)号：US5488002A

公开(公告)日：1996-01-30

申请号：US302199

申请日：1994-09-08

申请人： Koji Kimura ,  Shin-ichi Taka

发明人： Koji Kimura ,  Shin-ichi Taka

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/66272 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/035

摘要： Manufacturing a double polysilicon layer self-aligned type bipolar transistor. A polysilicon layer for emitter impurity diffusion is formed prior to the formation of a polysilicon layer for leading out a base. A first polysilicon layer containing impurities for base impurity diffusion is deposited over the entire surface of a semiconductor structure. After the first polysilicon layer is patterned into a predetermined shape, an intrinsic base layer is formed by thermally diffusing impurities from a base impurity diffusion source. Subsequently, a second polysilicon layer containing emitter impurities is formed over the base impurity diffusion source, and then patterning is performed such that the first and second polysilicon layers remain in a region narrower than the base impurity diffusion source. Thereafter, an emitter layer is formed by thermal diffusion.

摘要翻译： 制造双晶硅层自对准型双极晶体管。 在形成用于引出基底的多晶硅层之前，形成用于发射体杂质扩散的多晶硅层。 含有用于基底杂质扩散的杂质的第一多晶硅层沉积在半导体结构的整个表面上。 在将第一多晶硅层图案化成预定形状之后，通过从杂质扩散源热扩散杂质形成本征基极层。 随后，在基极杂质扩散源上形成含有发射极杂质的第二多晶硅层，然后进行图案化，使得第一和第二多晶硅层保持在比基极杂质扩散源窄的区域。 此后，通过热扩散形成发射极层。

公开(公告)号：US5356821A

公开(公告)日：1994-10-18

申请号：US104907

申请日：1993-08-12

申请人： Hiroshi Naruse ,  Shin-ichi Taka

发明人： Hiroshi Naruse ,  Shin-ichi Taka

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/49 ,  H01L29/737 ,  H01L21/265

CPC分类号： H01L29/7378 ,  H01L21/8248 ,  H01L21/8249 ,  H01L29/4966 ,  Y10S148/009

摘要： A semiconductor integrated circuit according to the present invention comprises a semiconductor substrate, a plurality of MOS field effect transistors each formed on a surface region of the semiconductor substrate and having source and drain regions, a gate insulating film formed on a region between the source and drain regions, and a gate electrode formed on the gate insulating film. The gate electrode includes a polycrystalline SiGe-mixed crystal which is expressed by Si.sub.1-x Ge.sub.x (1>x>0).

摘要翻译： 根据本发明的半导体集成电路包括半导体衬底，多个MOS场效应晶体管，其各自形成在半导体衬底的表面区域上并具有源极和漏极区，栅极绝缘膜形成在源极和源极之间的区域上 漏极区域和形成在栅极绝缘膜上的栅电极。 栅电极包括由Si1-xGex（1> x> 0）表示的多晶SiGe混合晶体。

公开(公告)号：US5244533A

公开(公告)日：1993-09-14

申请号：US815786

申请日：1992-01-02

申请人： Koji Kimura ,  Shin-ichi Taka

发明人： Koji Kimura ,  Shin-ichi Taka

IPC分类号： H01L21/331 ,  H01L29/10

CPC分类号： H01L29/66272 ,  H01L29/1004 ,  Y10S148/01 ,  Y10S148/124

摘要： According to this invention, in a method of manufacturing a bipolar transistor, a first oxide film, a nitride film, a first polysilicon film containing boron, and a second oxide film are formed on a substrate. A first opening is formed in the second oxide film and the first polysilicon film. The nitride film and the first oxide film are etched in and near the first opening to form overhung portions between the substrate and the first semiconductor film around the first opening. A second polysilicon film for burying the overhung portions is formed on the entire surface of the resultant structure. Thereafter, boron in the second polysilicon film is thermally diffused in the substrate to form an external base region and a link region. The second polysilicon film is etched to leave the second polysilicon film at only the overhung portions. After an internal base region formed in the substrate. Thereafter, an emitter region formed in the internal base region.

摘要翻译： 根据本发明，在制造双极晶体管的方法中，在基板上形成第一氧化膜，氮化物膜，含有硼的第一多晶硅膜和第二氧化物膜。 在第二氧化物膜和第一多晶硅膜中形成第一开口。 在第一开口内和附近蚀刻氮化物膜和第一氧化物膜，以在第一开口周围的基板和第一半导体膜之间形成悬垂部分。 用于掩埋悬臂部分的第二多晶硅膜形成在所得结构的整个表面上。 此后，第二多晶硅膜中的硼在衬底中热扩散以形成外部基极区域和连接区域。 蚀刻第二多晶硅膜以仅在悬垂部分离开第二多晶硅膜。 在形成在衬底中的内部基极区域之后。 此后，形成在内部基极区域中的发射极区域。