公开(公告)号：US4717682A

公开(公告)日：1988-01-05

申请号：US830928

申请日：1986-02-19

申请人： Shin-ichi Taka ,  Jiro Ohshima ,  Masahiro Abe ,  Masaharu Aoyama

发明人： Shin-ichi Taka ,  Jiro Ohshima ,  Masahiro Abe ,  Masaharu Aoyama

IPC分类号： H01L21/76 ,  H01L21/265 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/283

CPC分类号： H01L21/743

摘要： A method of manufacturing a semiconductor device, comprising the steps of sequentially forming a buried region and an epitaxial layer on a major surface of a semiconductor substrate, forming a conductive layer along an annular trench extending to the buried region, filling the annular trench with an insulating material and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench. In this method, the step of forming the conductive layer along the annular trench is carried out by the steps of forming an annular trench extending through said buried region, and depositing a conductive layer on only a side wall surface of said annular trench.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底的主表面上依次形成掩埋区域和外延层，沿着延伸到掩埋区域的环形沟槽形成导电层，用环形沟槽填充 绝缘材料，并在由所述掩埋区域围绕的所述外延层中形成功能元件，并在所述环形沟槽内形成所述绝缘材料。 在该方法中，沿着环形沟槽形成导电层的步骤是通过形成延伸穿过所述掩埋区域的环形沟槽以及仅在所述环形沟槽的侧壁表面上沉积导电层的步骤来执行的。

公开(公告)号：US4766086A

公开(公告)日：1988-08-23

申请号：US20758

申请日：1987-03-02

申请人： Jiro Ohshima ,  Shin-ichi Taka ,  Toshiyo Ito ,  Masaharu Aoyama

发明人： Jiro Ohshima ,  Shin-ichi Taka ,  Toshiyo Ito ,  Masaharu Aoyama

IPC分类号： H01L29/73 ,  H01L21/316 ,  H01L21/322 ,  H01L21/331 ,  H01L21/761 ,  H01L29/732 ,  H01L21/265 ,  H01L21/225

CPC分类号： H01L21/3221 ,  H01L21/761 ,  Y10S148/024

摘要： In a method of manufacturing a semiconductor device according to the present invention, a given position of a thermal oxide film formed on a monocrystalline silicon layer is opened to expose a surface of the monocrystalline silicon layer to serve as a getter site, a polycrystalline silicon layer is deposited on the thermal oxide film and the surface of the monocrystalline silicon layer, and the polycrystalline silicon layer is oxidized to convert the surface of the monocrystalline silicon layer directly contacting the polycrystalline silicon layer into an oxide film by thermal oxidation. That is, the position of interface between the oxide film and the monocrystalline silicon layer is shifted into the original monocrystalline silicon layer. During thermal oxidation of the polycrystalline silicon layer, a plurality of crystal defects to serve as getter sites are generated deeper than those generated by a conventional implagetter method in the monocrystalline silicon layer. In addition, the crystal defects generated in the manner described above do not extend to the surrounding region by subsequent annealing so that a region of the crystal defects is limited.

摘要翻译： 在根据本发明的半导体器件的制造方法中，形成在单晶硅层上的热氧化膜的给定位置被打开以暴露单晶硅层的表面以用作吸气部位，多晶硅层 沉积在热氧化膜和单晶硅层的表面上，并且多晶硅层被氧化，以通过热氧化将直接与多晶硅层接触的单晶硅层的表面转化为氧化膜。 也就是说，氧化膜和单晶硅层之间的界面的位置被转移到原始的单晶硅层中。 在多晶硅层的热氧化过程中，产生比用于单晶硅层中常规的投影仪方法产生的多个晶体缺陷作为吸气位置。 此外，以上述方式产生的晶体缺陷通过随后的退火不会延伸到周围区域，使得晶体缺陷的区域受到限制。

公开(公告)号：US4853760A

公开(公告)日：1989-08-01

申请号：US89959

申请日：1987-08-25

申请人： Masahiro Abe ,  Masaharu Aoyama ,  Jiro Ohshima ,  Takashi Ajima

发明人： Masahiro Abe ,  Masaharu Aoyama ,  Jiro Ohshima ,  Takashi Ajima

IPC分类号： H01L21/768 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/312 ,  H01L23/522

CPC分类号： H01L21/3105 ,  H01L21/31155 ,  H01L2924/0002

摘要： A semiconductor device has a passivation layer including a polyimide film. Argon ions are implanted in the polyimide film to convert it into an electrically stable insulating film.

摘要翻译： 半导体器件具有包括聚酰亚胺膜的钝化层。 将氩离子注入到聚酰亚胺膜中以将其转化为电稳定的绝缘膜。

公开(公告)号：US4853342A

公开(公告)日：1989-08-01

申请号：US300224

申请日：1989-01-24

申请人： Shin-ichi Taka ,  Jiro Ohshima

发明人： Shin-ichi Taka ,  Jiro Ohshima

IPC分类号： H01L29/73 ,  H01L21/20 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78

CPC分类号： H01L29/66287 ,  H01L21/2022 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1087 ,  H01L29/66242 ,  H01L29/66651 ,  H01L29/732 ,  Y10S148/01 ,  Y10S148/011

摘要： A transistor is formed according to the solid phase epitaxial growth which is one of the semiconductor integrated circuit device manufacturing techniques. A low-concentration impurity region is formed by selective solid phase epitaxial growth instead of using an epitaxial substrate. The solid phase epitaxial growth is performed twice, when a collector region is formed and when a base region is formed. The depth of collector and base regions are determined by the thickness of the solid phase growth layers, respectively.

摘要翻译： 根据作为半导体集成电路器件制造技术之一的固相外延生长形成晶体管。 通过选择性固相外延生长而不是使用外延衬底来形成低浓度杂质区。 当形成集电极区域和形成基极区域时，进行固相外延生长两次。 集电极和基极区域的深度分别由固相生长层的厚度决定。

公开(公告)号：US4975381A

公开(公告)日：1990-12-04

申请号：US492488

申请日：1990-03-12

申请人： Shin-ichi Taka ,  Jiro Ohshima

发明人： Shin-ichi Taka ,  Jiro Ohshima

IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L21/60 ,  H01L29/732

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L29/66272 ,  Y10S148/011 ,  Y10S148/124

摘要： This invention discloses a method of manufacturing an SST bipolar transistor, and the manufacturing method is capable of defining the size of a base region of the SST bipolar transistor. An insulating film and a spacer film serving as a spacer are sequentially formed in a bipolar transistor forming region on the main surface of a semiconductor substrate. Thereafter, the spacer film is patterned into a spacer film pattern for defining the size of the base region. A second insulating film, a base electrode pattern and a third insulating film are sequentially formed on the spacer film pattern. A first opening which reaches the spacer film pattern through the second insulating film, the base electrode pattern and the third insulating film is formed. The spacer film pattern is etched from the first opening to form a second opening having a diameter larger than that of the first opening. The insulating film exposed in the second opening is etched. The size of the base region on the major surface of the semiconductor substrate is defined by the size of the second opening.

摘要翻译： 本发明公开了一种制造SST双极型晶体管的方法，该制造方法能够限定SST双极型晶体管的基极区域的尺寸。 在半导体基板的主表面上的双极晶体管形成区域中依次形成用作间隔物的绝缘膜和间隔膜。 此后，间隔膜被图案化成用于限定基部区域的尺寸的间隔膜图案。 在间隔膜图案上依次形成第二绝缘膜，基极图案和第三绝缘膜。 形成通过第二绝缘膜到达间隔膜图案的第一开口，基极图案和第三绝缘膜。 从第一开口蚀刻间隔膜图案以形成直径大于第一开口直径的第二开口。 在第二开口中暴露的绝缘膜被蚀刻。 半导体基板的主表面上的基极区域的尺寸由第二开口的尺寸限定。

公开(公告)号：US5102826A

公开(公告)日：1992-04-07

申请号：US610216

申请日：1990-11-09

申请人： Jiro Ohshima ,  Shin-ichi Taka ,  Toshiyo Motozima ,  Hiroshi Naruse

发明人： Jiro Ohshima ,  Shin-ichi Taka ,  Toshiyo Motozima ,  Hiroshi Naruse

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/285

CPC分类号： H01L21/26506 ,  H01L21/28518 ,  Y10S148/106

摘要： According to the method of manufacturing a semiconductor device of the present invention, an insulation film is formed on a silicon substrate, and a resist film having a predetermined pattern is formed on the insulation film, followed by forming an opening on the insulation film with the resist film performing as a mask. Then, an impurity having conductivity are implanted into said silicon substrate with the resist film performing as a mask and silicon ions are implanted into the silicon substrate with the resist film performing as a mask. After that, the resist film is removed. Further, a refractory metal film which covers at least the opening is formed. Moveover, a diffusion layer which causes electrical activation of the impurity having conductivity is formed by annealing, followed by formation a silicide layer at where the surfaces of the silicon substrate and the metal film meet.

摘要翻译： 根据本发明的半导体器件的制造方法，在硅衬底上形成绝缘膜，在绝缘膜上形成具有预定图案的抗蚀剂膜，然后在绝缘膜上形成开口 作为掩模的抗蚀膜。 然后，将具有导电性的杂质注入到所述硅衬底中，并以抗蚀剂膜作为掩模将硅离子注入到硅衬底中，并将硅离子注入到硅衬底中。 之后，除去抗蚀剂膜。 此外，形成至少覆盖开口的难熔金属膜。 通过退火形成引起具有导电性的杂质的电活化的扩散层，随后在硅衬底和金属膜的表面相遇处形成硅化物层。

公开(公告)号：US4871685A

公开(公告)日：1989-10-03

申请号：US230823

申请日：1988-08-11

申请人： Shin-ichi Taka ,  Jiro Ohshima

发明人： Shin-ichi Taka ,  Jiro Ohshima

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L21/763 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L21/763 ,  Y10S148/01 ,  Y10S148/011

摘要： A metal layer is formed by selective CVD method on an emitter region formed by using a field oxide film as a mask. Opening for ion-implanting an impurity for forming external base region is formed in the field oxide film by utilizing the metal layer and a metal layer creep up a bird's beak of the field oxide film as masks. An impurity is doped in a semiconductor substrate through the opening formed in the field oxide film to form external base region. The distance between the emitter region and external base region is controlled by a length of the metal layer creep up the bird's beak.

摘要翻译： 通过选择性CVD法在通过使用场氧化膜作为掩模形成的发射极区域上形成金属层。 通过利用金属层在场氧化膜中形成用于离子注入用于形成外部基极区域的杂质的开口，并且金属层将场氧化膜的鸟喙蠕变成掩模。 通过形成在场氧化膜中的开口在半导体衬底中掺杂杂质以形成外部基极区。 发射极区域和外部基极区域之间的距离由金属层的长度在鸟的喙上蠕动控制。

公开(公告)号：US4334349A

公开(公告)日：1982-06-15

申请号：US155975

申请日：1980-06-03

申请人： Masaharu Aoyama ,  Jiro Ohshima ,  Toshio Yonezawa

发明人： Masaharu Aoyama ,  Jiro Ohshima ,  Toshio Yonezawa

IPC分类号： H01L21/3205 ,  H01L21/033 ,  H01L21/768 ,  H01L23/31 ,  H01L23/482 ,  H01L23/532 ,  H01L21/225 ,  B44C1/22 ,  H01L21/312

CPC分类号： H01L23/4827 ,  H01L21/033 ,  H01L21/76838 ,  H01L21/7688 ,  H01L23/3192 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

摘要： Disclosed is a method of producing a semiconductor device, comprising the steps of (a) forming a first insulating layer consisting of a lower silicon oxide film and an upper slicon nitride film on the surface of a semiconductor substrate, (b) forming a second insulating layer consisting of silicon oxide on the first insulating layer, (c) forming a third insulating layer consisting of silicon nitride on the second insulating layer, (d) selectively removing the third insulating layer so as to form a mask used for forming a hole for an interconnection electrode, (e) etching away the exposed portion of the second insulating layer by using the mask so as to form the hole for the interconnection electrode, (f) forming a conductive material layer on the entire surface of the structure obtained by step (e), a contact hole formed in the first insulating layer after step (a) or (e) being filled with the conductive material so as to allow the conductive material layer disposed on the first insulating layer to be connected to the semiconductor substrate, and (g) removing the second insulating layer by etching so as to lift-off the third insulating layer and the conductive material layer laminated on the second insulating layer, the remaining conductive materal layer providing the interconnection electrode.

摘要翻译： 公开了一种制造半导体器件的方法，包括以下步骤：（a）在半导体衬底的表面上形成由下部氧化硅膜和上部氮化硅膜构成的第一绝缘层，（b）形成第二绝缘体 在所述第一绝缘层上由氧化硅构成的层，（c）在所述第二绝缘层上形成由氮化硅构成的第三绝缘层，（d）选择性地除去所述第三绝缘层，以形成用于形成用于 互连电极，（e）通过使用掩模蚀刻掉第二绝缘层的暴露部分，以便形成用于互连电极的孔，（f）在通过步骤获得的结构的整个表面上形成导电材料层 （e）中，在步骤（a）或（e）之后形成在第一绝缘层中的接触孔填充有导电材料，以便允许设置在第一岛上的导电材料层 以及（g）通过蚀刻去除第二绝缘层，以便剥离层压在第二绝缘层上的第三绝缘层和导电材料层，剩余的导电侧层提供 互连电极。

公开(公告)号：US4404736A

公开(公告)日：1983-09-20

申请号：US319411

申请日：1981-11-09

申请人： Yutaka Koshino ,  Takashi Ajima ,  Jiro Ohshima ,  Masahiro Abe

发明人： Yutaka Koshino ,  Takashi Ajima ,  Jiro Ohshima ,  Masahiro Abe

IPC分类号： H01L21/316 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L23/3171 ,  H01L21/316 ,  H01L23/291 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/3511 ,  Y10S148/05 ,  Y10S148/085 ,  Y10S148/159 ,  Y10S438/928

摘要： A method for manufacturing a semiconductor device of mesa type comprises forming mesa recesses of predetermined depth around an element in the surface of a semiconductor body, forming on the back of semiconductor body a film for lessening the concentration of stress, filling glass powder into mesa recesses, and sintering glass powder to form glass insulators. According to the method of the present invention, cracks can be prevented from being caused in the semiconductor body and glass insulators formed in mesa recesses.

摘要翻译： 一种台面型半导体器件的制造方法包括在半导体本体的表面的元件周围形成预定深度的台面凹部，在半导体本体的背面形成用于减小应力集中的膜，将玻璃粉末填充到台面凹部 ，并烧结玻璃粉末以形成玻璃绝缘体。 根据本发明的方法，可以防止在形成在台面凹部中的半导体本体和玻璃绝缘体中产生裂纹。

公开(公告)号：US4502207A

公开(公告)日：1985-03-05

申请号：US562212

申请日：1983-12-16

申请人： Jiro Ohshima ,  Masahiro Abe ,  Yutaka Koshino

发明人： Jiro Ohshima ,  Masahiro Abe ,  Yutaka Koshino

IPC分类号： H01L21/3215 ,  H01L23/532 ,  H01L21/28

CPC分类号： H01L23/53219 ,  H01L21/3215 ,  H01L2924/0002 ,  Y10T428/12528

摘要： A wiring material of a semiconductor device, which comprises aluminum as a major component and at least a surface layer of the wiring layer is alloyed with boron and silicon. A method for forming a wiring material of a semiconductor device, which comprises the steps of: forming a wiring pattern comprising aluminum as a major component on a semiconductor element; and ion-implanting one of boron and a mixture of boron and silicon in the wiring pattern and alloying at least a surface layer of the wiring pattern to form an alloy layer containing aluminum, boron and silicon.

摘要翻译： 包含铝作为主要成分的半导体器件的布线材料和布线层的至少表面层与硼和硅合金化。 一种形成半导体器件布线材料的方法，包括以下步骤：在半导体元件上形成包含铝作为主要成分的布线图案; 并在布线图案中离子注入硼和硼与硅的混合物中的一种，并在布线图案的至少表面层合金化，形成含有铝，硼和硅的合金层。