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202 条记录 (耗时 0.032 秒)

    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5963467A

    公开(公告)日：1999-10-05

    申请号：US982457

    申请日：1997-12-02

    申请人： Shinichi Miyatake ,  Shigekazu Kase ,  Masayuki Nakamura ,  Masatoshi Hasegawa ,  Kazuhiko Kajigaya

    发明人： Shinichi Miyatake ,  Shigekazu Kase ,  Masayuki Nakamura ,  Masatoshi Hasegawa ,  Kazuhiko Kajigaya

    IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  G11C11/24

    CPC分类号： G11C11/22

    摘要： In a semiconductor memory device having a plurality of memory cells in which each memory cell is formed of an address selection MOSFET and an information storing capacitor and the plate voltage consisting of an intermediate potential is supplied to the common electrode of the information storing capacitor, the memory access is enabled by indirectly detecting that the plate voltage has reached a predetermined potential near a intermediate potential with the voltage detecting circuit or timer circuit, inhibiting the selecting operation of the word lines or precharging of the pair of bit lines to the intermediate potential when the plate voltage is lower than the predetermined potential, and then canceling the above inhibit condition after the plate voltage has reached the predetermined potential.

    摘要翻译： 在具有多个存储单元的半导体存储器件中，其中每个存储单元由地址选择MOSFET和信息存储电容器形成，并且由中间电位构成的板电压被提供给信息存储电容器的公共电极， 通过用电压检测电路或定时器电路间接地检测到板电压已经达到中间电位附近的预定电位，使得能够进行存储器访问，从而阻止字线的选择操作或将一对位线预充电到中间电位 板电压低于预定电位，然后在板电压达到预定电位之后取消上述禁止条件。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06178108B1

    公开(公告)日：2001-01-23

    申请号：US09258462

    申请日：1999-02-26

    申请人： Shinichi Miyatake ,  Shigekazu Kase ,  Masayuki Nakamura ,  Masatoshi Hasegawa ,  Kazuhiko Kajigaya

    发明人： Shinichi Miyatake ,  Shigekazu Kase ,  Masayuki Nakamura ,  Masatoshi Hasegawa ,  Kazuhiko Kajigaya

    IPC分类号： G11C1124

    CPC分类号： G11C11/22

    摘要： In a semiconductor memory device having a plurality of memory cells in which each memory cell is formed of an address selection MOSFET and an information storing capacitor and the plate voltage consisting of an intermediate potential is supplied to the common electrode of the information storing capacitor, the memory access is enabled by detecting indirect that the plate voltage has reached the predetermined potential near the intermediate potential with the voltage detecting circuit or timer circuit, inhibiting the selecting operation of the word lines or precharging the pair bit lines to the intermediate potential when the plate voltage is lower than the predetermined potential, and then canceling the above inhibit condition after the plate voltage has reached the predetermined potential.

    摘要翻译： 在具有多个存储单元的半导体存储器件中，其中每个存储单元由地址选择MOSFET和信息存储电容器形成，并且由中间电位构成的板电压被提供给信息存储电容器的公共电极， 通过检测间接使用电压检测电路或定时器电路使板电压达到中间电位附近的预定电位来启用存储器访问，当板的电压被抑制时，字线的选择操作或预先充电到中间电位 电压低于预定电位，然后在板电压达到预定电位后取消上述禁止条件。

    Dynamic memory
    3.
    发明授权
    Dynamic memory 失效
    动态内存

    公开(公告)号：US5905685A

    公开(公告)日：1999-05-18

    申请号：US951734

    申请日：1997-10-15

    申请人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

    发明人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

    IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

    CPC分类号： G11C11/4074 ,  G11C11/408 ,  G11C11/4087

    摘要： In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.

    摘要翻译： 在具有存储单元阵列的动态RAM中，其中动态存储单元布置在字线和一对位线中的一个位线之间的交叉点处，对应于电源电压的选择电平信号和对应于 低于电路接地电位的负电位被提供给字线。 通过由电路接地电位进行工作的读出放大器对一对位线读取的存储单元的信号和通过将电源电压降低等于地址选择MOSFET的阈值电压的量而形成的内部电压被放大。 动态RAM具有接收电源电压和电路接地电位的振荡器，以及接收由振荡器产生的振荡脉冲以产生负电位的电路。