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    Semiconductor integrated circuit device and process for manufacturing the same
    2.
    发明授权
    Semiconductor integrated circuit device and process for manufacturing the same 失效
    半导体集成电路器件及其制造方法

    公开(公告)号：US06423593B1

    公开(公告)日：2002-07-23

    申请号：US09943516

    申请日：2001-08-31

    申请人： Satoshi Yamamoto ,  Shinpei Iijima

    发明人： Satoshi Yamamoto ,  Shinpei Iijima

    IPC分类号： H01L218242

    CPC分类号： H01L21/76897 ,  C23C16/40 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/10814 ,  H01L28/55 ,  H01L28/60 ,  H01L28/91

    摘要： There is provided a technique for forming an Ru film on the bottom of a deep hole with a considerable film thickness for the lower electrode of an information storage capacity element in order to improve the yield of manufacturing DRAMs. The Ru film is formed on the side wall and the bottom of a deep hole as material for preparing the lower electrode of an information storage capacity element to be produced there under the condition of a gasification flow rate ratio of the raw materials ((Ru(C2H5C5H4)2/O2) is not less than 10%. Then, the ratio of the film thickness of the Ru film on the bottom “b” of the hole to the largest film thickness “a” of the Ru film in the hole is not less than 50%.

    摘要翻译： 为了提高DRAM的制造成本，提供了用于在信息存储电容元件的下部电极的深孔底部形成Ru膜的技术。 Ru膜形成在深孔的侧壁和底部作为用于制备在原料的气化流量比（（Ru（ C2H5C5H4）2 / O2）不小于10％，然后孔中底部的Ru膜厚度与孔中的Ru膜的最大膜厚“a”的比率为 不低于50％。

    Process for manufacturing a semiconductor memory device including a memory cell selecting transistor and a capacitor with metal electrodes
    3.
    发明授权
    Process for manufacturing a semiconductor memory device including a memory cell selecting transistor and a capacitor with metal electrodes 有权
    用于制造包括存储单元选择晶体管和具有金属电极的电容器的半导体存储器件的工艺

    公开(公告)号：US06649465B2

    公开(公告)日：2003-11-18

    申请号：US09943506

    申请日：2001-08-31

    申请人： Shinpei Iijima ,  Satoshi Yamamoto

    发明人： Shinpei Iijima ,  Satoshi Yamamoto

    IPC分类号： H01L218242

    CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L27/10885 ,  H01L28/55 ,  H01L28/91

    摘要： A technique is provided which is capable of forming a Ru film constituting a lower electrode of an information storing capacitive element in an aperture with high precision. After a Ru film is deposited, heat treatment is performed in a reducing atmosphere on a side wall and a bottom portion of a deep aperture in which the information storing capacitive element is formed. The deposition and heating of Ru films can be repeated to form a laminated structure of Ru films. As a result, it is possible to effectively remove impurities included in the Ru film, and to achieve fineness of the Ru film.

    摘要翻译： 提供了能够以高精度形成构成孔的信息存储电容元件的下电极的Ru膜的技术。 在沉积Ru膜之后，在形成有信息存储电容元件的深孔的侧壁和底部的还原气氛中进行热处理。 可以重复Ru膜的沉积和加热以形成Ru膜的层压结构。 结果，可以有效地除去Ru膜中所含的杂质，并且实现Ru膜的细度。

    Method of forming a ruthenium film by CVD
    5.
    发明授权
    Method of forming a ruthenium film by CVD 失效
    通过CVD形成钌膜的方法

    公开(公告)号：US06544835B2

    公开(公告)日：2003-04-08

    申请号：US10173159

    申请日：2002-06-18

    申请人： Satoshi Yamamoto ,  Shinpei Iijima

    发明人： Satoshi Yamamoto ,  Shinpei Iijima

    IPC分类号： H01L218242

    CPC分类号： H01L21/76897 ,  C23C16/40 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/10814 ,  H01L28/55 ,  H01L28/60 ,  H01L28/91

    摘要： There is provided a technique for forming an Ru film on the bottom of a deep hole with a considerable film thickness for the lower electrode of an information storage capacity element in order to improve the yield of manufacturing DRAMs. The Ru film is formed on the side wall and the bottom of a deep hole as material for preparing the lower electrode of an information storage capacity element to be produced there under the condition of a gasification flow rate ratio of the raw materials ((Ru(C2H5C5H4)2/O2) is not less than 10% Then, the ratio of the film thickness of the Ru film on the bottom “b” of the hole to the largest film thickness “a” of the Ru film in the hole is not less than 50%.

    摘要翻译： 为了提高DRAM的制造成本，提供了用于在信息存储电容元件的下部电极的深孔底部形成Ru膜的技术。 Ru膜形成在深孔的侧壁和底部作为用于制备在原料的气化流量比（（Ru（ C2H5C5H4）2 / O2）不小于10％然后，孔中底部“b”上的Ru膜的膜厚与孔中的Ru膜的最大膜厚“a”的比率不是 小于50％。

    Semiconductor memory device and method for manufacturing semiconductor memory device
    6.
    发明申请
    Semiconductor memory device and method for manufacturing semiconductor memory device 审中-公开
    半导体存储器件及半导体存储器件的制造方法

    公开(公告)号：US20060234510A1

    公开(公告)日：2006-10-19

    申请号：US11402061

    申请日：2006-04-12

    申请人： Shinpei Iijima

    发明人： Shinpei Iijima

    IPC分类号： H01L21/4763 ,  H01L21/311 ,  H01L21/302

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894

    摘要： According to an aspect of the present invention, there is provided a semiconductor memory device. The semiconductor memory device is provided with an insulator and a capacitor. The capacitor is provided with a lower electrode provided with an inner portion and an outer portion, a dielectric portion on the lower electrode, and an upper electrode on the dielectric portion. The inner portion is provided with a lower part and an upper part upwardly extending from the lower part. The insulator laterally holds the lower part. The outer portion is arranged on the insulator and is electrically connected with the upper part.

    摘要翻译： 根据本发明的一个方面，提供一种半导体存储器件。 半导体存储器件设置有绝缘体和电容器。 电容器设置有设置有内部部分和外部部分的下部电极，下部电极上的电介质部分和电介质部分上的上部电极。 内部具有从下部向上延伸的下部和上部。 绝缘体横向保持下部。 外部部分布置在绝缘体上并与上部电连接。

    Integrated circuit capacitor
    7.
    发明授权
    Integrated circuit capacitor 有权

    公开(公告)号：US06653676B2

    公开(公告)日：2003-11-25

    申请号：US09918228

    申请日：2001-07-30

    申请人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

    发明人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

    IPC分类号： H01L27108

    CPC分类号： H01L28/75 ,  H01L21/28518 ,  H01L21/76897 ,  H01L28/55 ,  H01L28/90

    摘要： The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.

    Capacitor and process for manufacturing the same
    10.
    发明授权
    Capacitor and process for manufacturing the same 失效
    电容器和制造过程相同

    公开(公告)号：US07667257B2

    公开(公告)日：2010-02-23

    申请号：US11585203

    申请日：2006-10-24

    申请人： Shinpei Iijima

    发明人： Shinpei Iijima

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L28/91

    摘要： Method for solving the problem caused when forming a crown-structure capacitor in a trench which is formed in an insulating film, and having difficulty in electrical by connecting a first upper electrode formed on the inside wall of the trench and a second upper electrode which is to be a plate because of the intervention of dielectric between the first and second upper electrodes. The conducting state of the first upper electrode and the plate upper electrode is ensured by utilizing a tantalum oxide film formed on a titanium nitride film, which is brought to a completely conducting state when heat treated. A crown structure is formed without removing the insulating film, in which a trench has been formed, by wet etching, whereby a stacked trench capacitor, which has double the capacity is provided while eliminating the collapse of the lower electrode or pair bit defect.

    摘要翻译： 用于解决在形成在绝缘膜中的沟槽中形成冠状结构电容器时引起的问题的方法，并且难以通过连接形成在沟槽的内壁上的第一上电极和第二上电极 由于第一和第二上部电极之间的电介质的介入而成为板。 通过利用形成在氮化钛膜上的氧化钽膜来确保第一上电极和板上电极的导电状态，当经过热处理时，其形成为完全导通状态。 通过湿式蚀刻，形成不形成沟槽的绝缘膜而形成凸面结构，由此提供具有双倍容量的叠层沟槽式电容器，同时消除了下部电极或对位缺陷的崩溃。