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公开(公告)号：US06661692B2
公开(公告)日：2003-12-09
申请号：US10179710
申请日：2002-06-24
申请人： Shinsuke Anzai , Kenji Kamei , Yasumichi Mori
发明人： Shinsuke Anzai , Kenji Kamei , Yasumichi Mori
IPC分类号： G11C506
CPC分类号： G11C29/80 , G11C15/00 , G11C15/046 , H01L27/0207
摘要： A semiconductor integrated circuit of the present invention includes: n first output circuits and m second output circuits which are provided such that adjacent first and second output circuits are spaced at a regular first pitch; and input circuits which are provided such that adjacent input circuits are spaced at a regular second pitch, in which the first and second output circuits are provided such that at least part of ones of the first and second output circuit blocks alternate with the other ones of the first and second output circuits and each of the first output circuits is connected to a corresponding one of input circuits by a first conductor line which is kept straight, and second conductor lines are connected to the second output circuits such that each second conductor line passes through a gap between the input circuits.
摘要翻译： 本发明的半导体集成电路包括：n个第一输出电路和m个第二输出电路，其被设置成使得相邻的第一和第二输出电路以规则的第一间距间隔开; 以及输入电路，其被设置为使得相邻输入电路以规则的第二间距间隔开，其中第一和第二输出电路被设置成使得第一和第二输出电路块中的至少一部分与其他 第一和第二输出电路和第一输出电路中的每一个通过保持直的第一导体线连接到相应的一个输入电路，并且第二导体线连接到第二输出电路，使得每个第二导线通过 通过输入电路之间的间隙。
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公开(公告)号：US20050174868A1
公开(公告)日：2005-08-11
申请号：US11051139
申请日：2005-02-04
申请人： Shinsuke Anzai , Yasumichi Mori
发明人： Shinsuke Anzai , Yasumichi Mori
CPC分类号： G11C16/28 , G11C11/5642 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C16/3436 , G11C2013/0054 , G11C2213/31
摘要： A nonvolatile semiconductor memory device comprises a readout circuit which reads data stored in a selected memory cell by applying predetermined voltage to the selected memory cell and a reference cell such that currents corresponding to the respective threshold voltage may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference cell. The readout circuit commonly uses the reference cell set in the same storage state for normal readout and for readout for program verification, and when the predetermined voltage is applied to the selected memory cell and the reference memory cell at the time of the readout for the program verification, it sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.
摘要翻译： 非易失性半导体存储器件包括读出电路，其通过向所选择的存储单元施加预定电压来读取存储在所选择的存储单元中的数据，以及参考单元，使得可以流过对应于相应阈值电压的电流，并且比较流过 选定的存储单元，电流在参考单元中流动。 读出电路通常使用相同存储状态的参考单元设置用于正常读出和用于程序验证的读出，并且当在用于程序的读出时将预定电压施加到所选存储单元和参考存储单元时 验证时，将参考存储单元的应用条件设置为使得其存储状态可以在程序状态方向上比在正常读出时的应用条件中更多地移位。
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公开(公告)号：US06947322B2
公开(公告)日：2005-09-20
申请号：US10630641
申请日：2003-07-29
申请人： Shinsuke Anzai , Yasumichi Mori , Hidehiko Tanaka
发明人： Shinsuke Anzai , Yasumichi Mori , Hidehiko Tanaka
IPC分类号： G06F12/16 , G11C11/56 , G11C16/00 , G11C16/02 , G11C16/06 , G11C16/28 , G11C29/00 , G11C29/04 , G11C16/04
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/28 , G11C29/70 , G11C2211/5623 , G11C2211/5641
摘要： A semiconductor memory device is provided, which comprising a memory cell array comprising a two-value memory region and a multi-value memory region, in which the two-value memory region comprises a plurality of memory cells each storing 1-bit data and the multi-value memory region comprises a plurality of memory cells each storing 2 or more-bit data, and a sense amplifier section common to data read of the two-value memory region and data read of the multi-value memory region, for reading data stored in a selected memory cell by comparing a potential of the selected memory cell with a reference potential.
摘要翻译： 提供一种半导体存储器件，其包括存储单元阵列，该存储单元阵列包括二值存储区域和多值存储器区域，其中该二值存储器区域包括多个存储单元，每个存储器单元存储1位数据， 多值存储区包括多个存储2位或更多比特数据的存储单元，以及读出两值存储区域的数据和多值存储器区域的数据读出共同的读出放大器单元，用于读取数据 通过将所选择的存储器单元的电位与参考电位进行比较来存储在所选存储单元中。
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公开(公告)号：US07088626B2
公开(公告)日：2006-08-08
申请号：US11055641
申请日：2005-02-09
申请人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
发明人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
IPC分类号： G11C7/00
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062 , G11C7/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5004 , G11C2207/063
摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
摘要翻译： 向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。 每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中 控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及 分别在输出节点和电流供应节点之间调整偏置电压。
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公开(公告)号：US07020037B2
公开(公告)日：2006-03-28
申请号：US11051139
申请日：2005-02-04
申请人： Shinsuke Anzai , Yasumichi Mori
发明人： Shinsuke Anzai , Yasumichi Mori
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C16/3436 , G11C2013/0054 , G11C2213/31
摘要： A nonvolatile semiconductor memory device includes a readout circuit which reads data stored in a selected memory cell by applying predetermined voltage to the selected memory cell and a reference cell such that currents corresponding to the respective threshold voltage may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference cell. The readout circuit commonly uses the reference cell set in the same storage state for normal readout and for readout for program verification, and when the predetermined voltage is applied to the selected memory cell and the reference memory cell at the time of the readout for the program verification, it sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.
摘要翻译： 非易失性半导体存储器件包括：读出电路，通过向所选择的存储单元施加预定电压，读取存储在所选择的存储单元中的数据;以及参考单元，使得与各个阈值电压相对应的电流可以流动， 选定的存储单元，电流在参考单元中流动。 读出电路通常使用相同存储状态的参考单元设置用于正常读出和用于程序验证的读出，并且当在用于程序的读出时将预定电压施加到所选择的存储单元和参考存储单元时 验证时，将参考存储单元的应用条件设置为使得其存储状态可以在程序状态方向上比在正常读出时的应用条件中更多地移位。
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公开(公告)号：US06930922B2
公开(公告)日：2005-08-16
申请号：US10630568
申请日：2003-07-29
CPC分类号： G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.
摘要翻译： 读取电路，用于从多个存储单元的一个存储单元读取数据，包括多个分割感测电路，每个分割感测电路经由多个感测线路中与之对应的感测线连接到该一个存储单元; 以及电流 - 电压转换电路，用于将流过每个感测线的电流转换成表示相应感测线的电位的感测电压。 每个分割感测电路包括用于经由相应的感测线路向一个存储单元提供电流的电流负载电路和用于感测相应感测线与多条参考线的对应参考线之间的电位差的读出放大器。 包括在至少一个分割感测电路中的电流负载电路具有与包括在另一个分割感测电路中的当前负载电路不同的电流供应能力。
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公开(公告)号：US20050174859A1
公开(公告)日：2005-08-11
申请号：US11055641
申请日：2005-02-09
申请人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
发明人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062 , G11C7/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5004 , G11C2207/063
摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
摘要翻译： 向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。 每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中 控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及 分别在输出节点和电流供应节点之间调整偏置电压。
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公开(公告)号：US20070230245A1
公开(公告)日：2007-10-04
申请号：US10589066
申请日：2005-02-09
申请人： Masahiko Watanabe , Yasumichi Mori
发明人： Masahiko Watanabe , Yasumichi Mori
IPC分类号： G11C29/04
摘要： A semiconductor storage device according to the present invention comprises one or more memory planes 8 comprising a plurality of memory blocks 9, and a block selection circuit for decoding an block address signal for selecting the memory block 9 from the memory plane 8 to select the memory block, generates a dummy block address for selecting a dummy block that is different from the selected block address and a defective block address of a defective block by a predetermined logical operation targeted for a specific partial bit in address bits of the selected block address when the defective block is contained in the memory plane. A bit line connected to the selected memory cell selected by the selected block address and a bit line in the dummy block are connected to differential input terminals of a sense amplifier circuit 9.
摘要翻译： 根据本发明的半导体存储装置包括一个或多个包括多个存储器块9的存储器平面8和一个块选择电路，用于解码用于从存储器平面8中选择存储器块9的块地址信号，以选择存储器 块，产生一个虚拟块地址，用于当所选择的块地址的地址位中的特定部分位的目标地址为预定逻辑运算时，选择不同于所选择的块地址的虚拟块和缺陷块的缺陷块地址， 缺陷块包含在存储器平面中。 连接到由选择的块地址选择的所选存储单元的位线和伪块中的位线连接到读出放大器电路9的差分输入端。
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公开(公告)号：US06442058B2
公开(公告)日：2002-08-27
申请号：US09834963
申请日：2001-04-13
申请人： Yasumichi Mori
发明人： Yasumichi Mori
IPC分类号： G11C1700
CPC分类号： G06F9/3822 , G06F9/26 , G06F9/261 , G06F9/268 , G06F9/30145 , G06F9/30181 , G06F9/30196 , G06F9/3814
摘要： A control circuit comprises an external command recognition section for recognizing an external command, the external command being an operation command input from outside the control circuit, an internal ROM bank including a plurality of storage regions, the internal ROM bank being used to store an internal code for achieving operations specified by the external command recognized by the external command recognition section, an internal ROM selection section for selecting a required storage region from the plurality of storage regions of the internal ROM bank in accordance with the external command recognized by the external command recognition section, a program counter for selecting and indicating an address of an internal command to be executed from a plurality of addresses of internal commands stored in the internal ROM bank, an internal command register for storing the internal command read from the internal ROM bank, and an internal command execution section for executing the internal command stored in the internal command register.
摘要翻译： 控制电路包括用于识别外部命令的外部命令识别部分，作为从控制电路外部输入的操作命令的外部命令，包括多个存储区域的内部ROM组，内部ROM组用于存储内部 用于实现由外部命令识别部识别的外部命令指定的操作的代码;内部ROM选择部分，用于根据由外部命令识别的外部命令从内部ROM组的多个存储区域中选择所需的存储区域 识别部分，用于从存储在内部ROM组中的多个内部命令的地址中选择和指示要执行的内部命令的地址的程序计数器，用于存储从内部ROM存储体读取的内部命令的内部命令寄存器， 以及用于执行in的内部命令执行部分 内部命令存储在内部命令寄存器中。
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10.发明授权公开(公告)号：US07460419B2
公开(公告)日：2008-12-02
申请号：US10589101
申请日：2005-02-09
申请人： Yasumichi Mori , Masahiko Watanabe
发明人： Yasumichi Mori , Masahiko Watanabe
CPC分类号： G11C29/76
摘要： A nonvolatile semiconductor storing device according to the present invention comprises a block replacing means for replacing a defective block with a redundant block when a memory block in a memory array is the defective block. The block replacing means includes an address translation circuit 10 for converting an inputted external block address into an internal block address by inverting an address bit corresponding to dissident of each address bit between a defective block address of the defective block and a redundant block address among address bits of the inputted external block address, and each of the memory blocks 5 is selected based on the internal block address after the translation of the external block address inputted from outside by the address translation circuit 10.
摘要翻译： 根据本发明的非易失性半导体存储装置包括：块存储器替换装置，用于在存储器阵列中的存储块是缺陷块时用冗余块替换缺陷块。 块替换装置包括地址转换电路10，用于将输入的外部块地址转换为内部块地址，通过将与缺陷块的缺陷块地址和地址中的冗余块地址之间的每个地址位的不同位相对应的地址位反相 基于由地址转换电路10从外部输入的外部块地址的转换之后的内部块地址来选择输入的外部块地址的比特，并且存储块5中的每一个被选择。
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