公开(公告)号：US20070230245A1

公开(公告)日：2007-10-04

申请号：US10589066

申请日：2005-02-09

申请人： Masahiko Watanabe ,  Yasumichi Mori

发明人： Masahiko Watanabe ,  Yasumichi Mori

IPC分类号： G11C29/04

CPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/28 ,  G11C29/76 ,  G11C29/82

摘要： A semiconductor storage device according to the present invention comprises one or more memory planes 8 comprising a plurality of memory blocks 9, and a block selection circuit for decoding an block address signal for selecting the memory block 9 from the memory plane 8 to select the memory block, generates a dummy block address for selecting a dummy block that is different from the selected block address and a defective block address of a defective block by a predetermined logical operation targeted for a specific partial bit in address bits of the selected block address when the defective block is contained in the memory plane. A bit line connected to the selected memory cell selected by the selected block address and a bit line in the dummy block are connected to differential input terminals of a sense amplifier circuit 9.

摘要翻译： 根据本发明的半导体存储装置包括一个或多个包括多个存储器块9的存储器平面8和一个块选择电路，用于解码用于从存储器平面8中选择存储器块9的块地址信号，以选择存储器 块，产生一个虚拟块地址，用于当所选择的块地址的地址位中的特定部分位的目标地址为预定逻辑运算时，选择不同于所选择的块地址的虚拟块和缺陷块的缺陷块地址， 缺陷块包含在存储器平面中。 连接到由选择的块地址选择的所选存储单元的位线和伪块中的位线连接到读出放大器电路9的差分输入端。

公开(公告)号：US07460419B2

公开(公告)日：2008-12-02

申请号：US10589101

申请日：2005-02-09

申请人： Yasumichi Mori ,  Masahiko Watanabe

发明人： Yasumichi Mori ,  Masahiko Watanabe

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/76

摘要： A nonvolatile semiconductor storing device according to the present invention comprises a block replacing means for replacing a defective block with a redundant block when a memory block in a memory array is the defective block. The block replacing means includes an address translation circuit 10 for converting an inputted external block address into an internal block address by inverting an address bit corresponding to dissident of each address bit between a defective block address of the defective block and a redundant block address among address bits of the inputted external block address, and each of the memory blocks 5 is selected based on the internal block address after the translation of the external block address inputted from outside by the address translation circuit 10.

摘要翻译： 根据本发明的非易失性半导体存储装置包括：块存储器替换装置，用于在存储器阵列中的存储块是缺陷块时用冗余块替换缺陷块。 块替换装置包括地址转换电路10，用于将输入的外部块地址转换为内部块地址，通过将与缺陷块的缺陷块地址和地址中的冗余块地址之间的每个地址位的不同位相对应的地址位反相 基于由地址转换电路10从外部输入的外部块地址的转换之后的内部块地址来选择输入的外部块地址的比特，并且存储块5中的每一个被选择。

公开(公告)号：US07430144B2

公开(公告)日：2008-09-30

申请号：US10589066

申请日：2005-02-09

申请人： Masahiko Watanabe ,  Yasumichi Mori

发明人： Masahiko Watanabe ,  Yasumichi Mori

IPC分类号： G11C7/00

CPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/28 ,  G11C29/76 ,  G11C29/82

摘要： A semiconductor storage device according to the present invention comprises one or more memory planes 8 comprising a plurality of memory blocks 9, and a block selection circuit for decoding an block address signal for selecting the memory block 9 from the memory plane 8 to select the memory block, generates a dummy block address for selecting a dummy block that is different from the selected block address and a defective block address of a defective block by a predetermined logical operation targeted for a specific partial bit in address bits of the selected block address when the defective block is contained in the memory plane. A bit line connected to the selected memory cell selected by the selected block address and a bit line in the dummy block are connected to differential input terminals of a sense amplifier circuit 9.

摘要翻译： 根据本发明的半导体存储装置包括一个或多个包括多个存储器块9的存储器平面8和一个块选择电路，用于解码用于从存储器平面8中选择存储器块9的块地址信号，以选择存储器 块，产生一个虚拟块地址，用于当所选择的块地址的地址位中的特定部分位的目标地址为预定逻辑运算时，选择不同于所选择的块地址的虚拟块和缺陷块的缺陷块地址， 缺陷块包含在存储器平面中。 连接到由选择的块地址选择的所选存储单元的位线和伪块中的位线连接到读出放大器电路9的差分输入端。

公开(公告)号：US07088626B2

公开(公告)日：2006-08-08

申请号：US11055641

申请日：2005-02-09

申请人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Masahiko Watanabe ,  Shinsuke Anzai ,  Takeshi Nojima ,  Munetaka Masaki

发明人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Masahiko Watanabe ,  Shinsuke Anzai ,  Takeshi Nojima ,  Munetaka Masaki

IPC分类号： G11C7/00

CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C7/062 ,  G11C7/12 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/063

摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.

摘要翻译： 向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。 每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中 控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及 分别在输出节点和电流供应节点之间调整偏置电压。

公开(公告)号：US07184334B2

公开(公告)日：2007-02-27

申请号：US11051346

申请日：2005-02-04

申请人： Masahiko Watanabe ,  Yasumichi Mori

发明人： Masahiko Watanabe ,  Yasumichi Mori

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C13/0028 ,  G11C13/0007 ,  G11C29/26 ,  G11C29/76 ,  G11C2029/2602 ,  G11C2213/31

摘要： A semiconductor memory device comprises at least one memory plane in which a plurality of memory blocks are arranged, and a block decoder circuit which decodes a block address signal for selecting the memory block from the memory plane and outputs block selection signals for selecting the memory block, as well as puts all of the block selection signals in a selected state and output them in a predetermined test mode, and a block selection signal inversion circuit which inverts or non-inverts signal levels of the block selection signals.

摘要翻译： 半导体存储器件包括至少一个其中布置有多个存储器块的存储器平面;以及块解码器电路，用于解码用于从存储器平面选择存储块的块地址信号，并输出用于选择存储块的块选择信号 并且将所有块选择信号置于选择状态并以预定的测试模式输出;以及块选择信号反相电路，其对块选择信号的信号电平进行反相或非反相。

公开(公告)号：US20050174862A1

公开(公告)日：2005-08-11

申请号：US11051346

申请日：2005-02-04

申请人： Masahiko Watanabe ,  Yasumichi Mori

发明人： Masahiko Watanabe ,  Yasumichi Mori

IPC分类号： G11C16/02 ,  G11C8/12 ,  G11C11/15 ,  G11C13/00 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/26 ,  G11C29/56 ,  G11C7/00

CPC分类号： G11C13/0028 ,  G11C13/0007 ,  G11C29/26 ,  G11C29/76 ,  G11C2029/2602 ,  G11C2213/31

摘要： A semiconductor memory device comprises at least one memory plane in which a plurality of memory blocks are arranged, and a block decoder circuit which decodes a block address signal for selecting the memory block from the memory plane and outputs block selection signals for selecting the memory block, as well as puts all of the block selection signals in a selected state and output them in a predetermined test mode, and a block selection signal inversion circuit which inverts or non-inverts signal levels of the block selection signals.

摘要翻译： 半导体存储器件包括至少一个其中布置有多个存储器块的存储器平面;以及块解码器电路，用于解码用于从存储器平面选择存储块的块地址信号，并输出用于选择存储块的块选择信号 并且将所有块选择信号置于选择状态并以预定的测试模式输出;以及块选择信号反相电路，其对块选择信号的信号电平进行反相或非反相。

公开(公告)号：US20070279984A1

公开(公告)日：2007-12-06

申请号：US10589101

申请日：2005-02-09

申请人： Yasumichi Mori ,  Masahiko Watanabe

发明人： Yasumichi Mori ,  Masahiko Watanabe

IPC分类号： G11C11/34

CPC分类号： G11C29/76

摘要： A nonvolatile semiconductor storing device according to the present invention comprises a block replacing means for replacing a defective block with a redundant block when a memory block in a memory array is the defective block. The block replacing means includes an address translation circuit 10 for converting an inputted external block address into an internal block address by inverting an address bit corresponding to dissident of each address bit between a defective block address of the defective block and a redundant block address among address bits of the inputted external block address, and each of the memory blocks 5 is selected based on the internal block address after the translation of the external block address inputted from outside by the address translation circuit 10.

摘要翻译： 根据本发明的非易失性半导体存储装置包括：块存储器替换装置，用于在存储器阵列中的存储块是缺陷块时用冗余块替换缺陷块。 块替换装置包括地址转换电路10，用于将输入的外部块地址转换为内部块地址，通过将与缺陷块的缺陷块地址和地址中的冗余块地址之间的每个地址位的不同位相对应的地址位反相 基于由地址转换电路10从外部输入的外部块地址的转换之后的内部块地址来选择输入的外部块地址的比特，并且存储块5中的每一个被选择。

公开(公告)号：US20050174859A1

公开(公告)日：2005-08-11

申请号：US11055641

申请日：2005-02-09

申请人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Masahiko Watanabe ,  Shinsuke Anzai ,  Takeshi Nojima ,  Munetaka Masaki

发明人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Masahiko Watanabe ,  Shinsuke Anzai ,  Takeshi Nojima ,  Munetaka Masaki

IPC分类号： G11C16/06 ,  G11C7/06 ,  G11C7/12 ,  G11C16/28 ,  G11C29/02 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C7/062 ,  G11C7/12 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/063

摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.

摘要翻译： 向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。 每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中 控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及 分别在输出节点和电流供应节点之间调整偏置电压。

公开(公告)号：US20050174868A1

公开(公告)日：2005-08-11

申请号：US11051139

申请日：2005-02-04

申请人： Shinsuke Anzai ,  Yasumichi Mori

发明人： Shinsuke Anzai ,  Yasumichi Mori

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C13/00 ,  G11C16/06 ,  G11C16/28 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/28 ,  G11C11/5642 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C16/3436 ,  G11C2013/0054 ,  G11C2213/31

摘要： A nonvolatile semiconductor memory device comprises a readout circuit which reads data stored in a selected memory cell by applying predetermined voltage to the selected memory cell and a reference cell such that currents corresponding to the respective threshold voltage may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference cell. The readout circuit commonly uses the reference cell set in the same storage state for normal readout and for readout for program verification, and when the predetermined voltage is applied to the selected memory cell and the reference memory cell at the time of the readout for the program verification, it sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.

摘要翻译： 非易失性半导体存储器件包括读出电路，其通过向所选择的存储单元施加预定电压来读取存储在所选择的存储单元中的数据，以及参考单元，使得可以流过对应于相应阈值电压的电流，并且比较流过 选定的存储单元，电流在参考单元中流动。 读出电路通常使用相同存储状态的参考单元设置用于正常读出和用于程序验证的读出，并且当在用于程序的读出时将预定电压施加到所选存储单元和参考存储单元时 验证时，将参考存储单元的应用条件设置为使得其存储状态可以在程序状态方向上比在正常读出时的应用条件中更多地移位。

公开(公告)号：US06947322B2

公开(公告)日：2005-09-20

申请号：US10630641

申请日：2003-07-29

申请人： Shinsuke Anzai ,  Yasumichi Mori ,  Hidehiko Tanaka

发明人： Shinsuke Anzai ,  Yasumichi Mori ,  Hidehiko Tanaka

IPC分类号： G06F12/16 ,  G11C11/56 ,  G11C16/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/28 ,  G11C29/00 ,  G11C29/04 ,  G11C16/04

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C16/28 ,  G11C29/70 ,  G11C2211/5623 ,  G11C2211/5641

摘要： A semiconductor memory device is provided, which comprising a memory cell array comprising a two-value memory region and a multi-value memory region, in which the two-value memory region comprises a plurality of memory cells each storing 1-bit data and the multi-value memory region comprises a plurality of memory cells each storing 2 or more-bit data, and a sense amplifier section common to data read of the two-value memory region and data read of the multi-value memory region, for reading data stored in a selected memory cell by comparing a potential of the selected memory cell with a reference potential.

摘要翻译： 提供一种半导体存储器件，其包括存储单元阵列，该存储单元阵列包括二值存储区域和多值存储器区域，其中该二值存储器区域包括多个存储单元，每个存储器单元存储1位数据， 多值存储区包括多个存储2位或更多比特数据的存储单元，以及读出两值存储区域的数据和多值存储器区域的数据读出共同的读出放大器单元，用于读取数据 通过将所选择的存储器单元的电位与参考电位进行比较来存储在所选存储单元中。