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1.发明申请公开(公告)号：US20100019337A1
公开(公告)日：2010-01-28
申请号：US12575910
申请日：2009-10-08
IPC分类号： H01L31/0232 , H01L31/0352
CPC分类号： H01L31/035281 , H01L21/32136 , H01L21/32137 , H01L27/14643 , Y02E10/50
摘要： An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.
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2.发明申请公开(公告)号：US20070278606A1
公开(公告)日：2007-12-06
申请号：US11737477
申请日：2007-04-19
IPC分类号： H01L31/075 , H01L31/18
CPC分类号： H01L31/035281 , H01L21/32136 , H01L21/32137 , H01L27/14643 , Y02E10/50
摘要： An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.
摘要翻译： 本发明的目的是提供一种具有不同锥角的侧面的光电转换元件，该光电转换元件逐步进行光电转换层的蚀刻。 与pn光电二极管相比，pin光电二极管具有高响应速度，但是具有大的暗电流的缺点。 认为暗电流的一个原因是通过在蚀刻中产生并沉积在光电转换层的侧表面上的蚀刻残余物导电。 光电转换元件的泄漏电流通过形成侧表面具有两个不同的锥形形状的结构而降低，通常具有均匀的表面，使得光电转换层具有p层的侧表面和侧表面 的n层，它们不在同一平面。
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3.发明申请公开(公告)号：US20100276773A1
公开(公告)日：2010-11-04
申请号：US12834040
申请日：2010-07-12
IPC分类号： H01L31/0216 , H01L31/0232 , H01L31/0352 , H01L31/105
CPC分类号： H01L31/035281 , H01L21/32136 , H01L21/32137 , H01L27/14643 , Y02E10/50
摘要： An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.
摘要翻译： 本发明的目的是提供一种具有不同锥角的侧面的光电转换元件，该光电转换元件逐步进行光电转换层的蚀刻。 与pn光电二极管相比，pin光电二极管具有高响应速度，但是具有大的暗电流的缺点。 认为暗电流的一个原因是通过在蚀刻中产生并沉积在光电转换层的侧表面上的蚀刻残渣导电。 光电转换元件的泄漏电流通过形成侧表面具有两个不同的锥形形状的结构而降低，通常具有均匀的表面，使得光电转换层具有p层的侧表面和侧表面 的n层，它们不在同一平面。
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公开(公告)号：US20120319101A1
公开(公告)日：2012-12-20
申请号：US13484742
申请日：2012-05-31
申请人： Shinya SASAGAWA , Hiroshi FUJIKI , Yoshinori IEDA
发明人： Shinya SASAGAWA , Hiroshi FUJIKI , Yoshinori IEDA
IPC分类号： H01L21/36 , H01L29/786
CPC分类号： H01L29/66969 , H01L21/02164 , H01L21/02178 , H01L21/02554 , H01L21/02565 , H01L21/47573 , H01L29/41733 , H01L29/66742 , H01L29/7869
摘要： A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.
摘要翻译： 与氧化物半导体膜和第二绝缘膜接触的第一绝缘膜依次层叠在包含氧化物半导体膜的晶体管的电极膜上，在第二绝缘膜上形成蚀刻掩模， 通过蚀刻第一绝缘膜的一部分和第二绝缘膜的一部分形成电极膜，将暴露于电极膜的开口部暴露于氩等离子体中，除去蚀刻掩模，并且在开口中形成导电膜 部分暴露电极膜。 第一绝缘膜是其氧气通过加热部分释放的绝缘膜。 第二绝缘膜比第一绝缘膜不易蚀刻，并且具有比第一绝缘膜更低的透气性。
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公开(公告)号：US20120319100A1
公开(公告)日：2012-12-20
申请号：US13483078
申请日：2012-05-30
申请人： Kyoko YOSHIOKA , Junichi KOEZUKA , Shinji OHNO , Yuichi SATO , Shinya SASAGAWA
发明人： Kyoko YOSHIOKA , Junichi KOEZUKA , Shinji OHNO , Yuichi SATO , Shinya SASAGAWA
IPC分类号： H01L29/786 , H01L21/44
CPC分类号： H01L29/7869 , H01L21/324 , H01L29/66969
摘要： A miniaturized semiconductor device in which an increase in power consumption is suppressed and a method for manufacturing the semiconductor device are provided. A highly reliable semiconductor device having stable electric characteristics and a method for manufacturing the semiconductor device are provided. An oxide semiconductor film is irradiated with ions accelerated by an electric field in order to reduce the average surface roughness of a surface of the oxide semiconductor film. Consequently, an increase in the leakage current and power consumption of a transistor can be suppressed. Moreover, by performing heat treatment so that the oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to the surface of the oxide semiconductor film, a change in electric characteristics of the oxide semiconductor film due to irradiation with visible light or ultraviolet light can be suppressed.
摘要翻译： 提供抑制功耗增加的小型化半导体装置及其制造方法。 提供了一种具有稳定电特性的高度可靠的半导体器件及其半导体器件的制造方法。 为了降低氧化物半导体膜的表面的平均表面粗糙度，用电场加速的离子照射氧化物半导体膜。 因此，可以抑制晶体管的漏电流和功耗的增加。 此外，通过进行热处理使得氧化物半导体膜包括具有与氧化物半导体膜的表面基本垂直的c轴的晶体，由于可见光或紫外线的照射而导致的氧化物半导体膜的电特性的变化 可以抑制。
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公开(公告)号：US20120286261A1
公开(公告)日：2012-11-15
申请号：US13466583
申请日：2012-05-08
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L21/8252 , H01L21/8256 , H01L27/0605 , H01L27/1225 , H01L29/78603 , H01L29/7869 , H01L29/78696
摘要： In a transistor including a wide band gap semiconductor layer as a semiconductor layer, a wide band gap semiconductor layer is separated into an island shape by an insulating layer with passivation properties for preventing atmospheric components from permeating. The edge portion of the island shape wide band gap semiconductor layer is in contact with the insulating film; thus, moisture or atmospheric components can be prevented from entering from the edge portion of the semiconductor layer to the wide band gap semiconductor layer.
摘要翻译： 在包括作为半导体层的宽带隙半导体层的晶体管中，通过具有防止大气成分渗透的钝化特性的绝缘层将宽带隙半导体层分离成岛状。 岛状宽带隙半导体层的边缘部分与绝缘膜接触; 因此，可以防止水分或大气成分从半导体层的边缘部分进入宽带隙半导体层。
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公开(公告)号：US20120193625A1
公开(公告)日：2012-08-02
申请号：US13357902
申请日：2012-01-25
申请人： Shinya SASAGAWA , Motomu KURATA
发明人： Shinya SASAGAWA , Motomu KURATA
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66969 , H01L21/441 , H01L29/41733 , H01L29/7869
摘要： An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.
摘要翻译： 本发明的目的是提供一种在保持有利特性的同时减小缺陷并实现小型化的半导体器件。 形成半导体层; 在半导体层上形成第一导电层; 使用第一抗蚀剂掩模蚀刻第一导电层以形成具有凹部的第二导电层; 第一抗蚀剂掩模的尺寸减小以形成第二抗蚀剂掩模; 使用第二抗蚀剂掩模蚀刻第二导电层，以形成在周边具有锥形形状的突出部分的源极和漏极; 在源极和漏极上形成栅极绝缘层以与半导体层的一部分接触; 并且栅极电极形成在栅极绝缘层上方并与半导体层重叠的部分。
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公开(公告)号：US20120061670A1
公开(公告)日：2012-03-15
申请号：US13220736
申请日：2011-08-30
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1262 , H01L21/44 , H01L27/1214 , H01L27/1218 , H01L27/1225 , H01L27/1288 , H01L29/66742 , H01L29/66969 , H01L29/7869
摘要： Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.
摘要翻译： 描述了一种用于制造半导体器件的方法。 在绝缘膜上形成掩模，并且掩模的尺寸减小。 使用尺寸减小的掩模形成具有突起的绝缘膜，并且使用具有突起的绝缘膜形成沟道长度减小的晶体管。 此外，在制造晶体管时，在与微细突起的顶面重叠的栅极绝缘膜的表面上进行平坦化处理。 因此，晶体管可以高速运转，可提高可靠性。 此外，绝缘膜被加工成具有突起的形状，由此可以以自对准的方式形成源电极和漏电极。
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公开(公告)号：US20120012836A1
公开(公告)日：2012-01-19
申请号：US13174960
申请日：2011-07-01
IPC分类号： H01L29/786 , H01L21/44 , H01L21/336
CPC分类号： H01L29/66969 , H01L22/14 , H01L27/088 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/45 , H01L29/4908 , H01L29/7869
摘要： When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.
摘要翻译： 当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。 在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。
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公开(公告)号：US20120003797A1
公开(公告)日：2012-01-05
申请号：US13159804
申请日：2011-06-14
IPC分类号： H01L21/336
CPC分类号： H01L29/7869 , H01L29/45 , H01L29/66969
摘要： When a transistor including a conductive layer having a three-layer structure is manufactured, three-stage etching is performed. In the first etching process, an etching method in which the etching rates for the second film and the third film are high is employed, and the first etching process is performed until the first film is at least exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. In the third etching process, an etching method in which the etching rates for the first to the third films are higher than those in the second etching process is preferably employed.
摘要翻译： 当制造包括具有三层结构的导电层的晶体管时，进行三级蚀刻。 在第一蚀刻工艺中，采用其中第二膜和第三膜的蚀刻速率高的蚀刻方法，并且执行第一蚀刻处理直到第一膜至少暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 在第三蚀刻工艺中，优选使用其中第一至第三膜的蚀刻速率高于第二蚀刻工艺中的蚀刻速率的蚀刻方法。
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