公开(公告)号：US20110207269A1

公开(公告)日：2011-08-25

申请号：US13026520

申请日：2011-02-14

申请人： Shinya SASAGAWA ,  Masashi TSUBUKU ,  Hitoshi NAKAYAMA ,  Daigo SHIMADA

发明人： Shinya SASAGAWA ,  Masashi TSUBUKU ,  Hitoshi NAKAYAMA ,  Daigo SHIMADA

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/66969 ,  H01L29/7869

摘要： A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.

摘要翻译： 晶体管通过以下方法制造：包括：形成第一布线层; 形成第一绝缘膜以覆盖所述第一布线层; 在所述第一绝缘膜上形成半导体层; 在半导体层上形成导电膜; 并且对所述导电膜进行蚀刻的至少两个步骤以形成彼此分离的第二布线层，其中所述两个蚀刻步骤至少包括在导电膜的蚀刻速率为 高于半导体层的蚀刻速率，以及在导电膜和半导体层的蚀刻速率高于第一蚀刻工艺的蚀刻速率的条件下进行的第二蚀刻工艺。

公开(公告)号：US20120012836A1

公开(公告)日：2012-01-19

申请号：US13174960

申请日：2011-07-01

申请人： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Masashi TSUBUKU ,  Daigo SHIMADA

发明人： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Masashi TSUBUKU ,  Daigo SHIMADA

IPC分类号： H01L29/786 ,  H01L21/44 ,  H01L21/336

CPC分类号： H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

摘要： When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

摘要翻译： 当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。 在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。

公开(公告)号：US20120003797A1

公开(公告)日：2012-01-05

申请号：US13159804

申请日：2011-06-14

申请人： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Masashi TSUBUKU ,  Daigo SHIMADA

发明人： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Masashi TSUBUKU ,  Daigo SHIMADA

IPC分类号： H01L21/336

CPC分类号： H01L29/7869 ,  H01L29/45 ,  H01L29/66969

摘要： When a transistor including a conductive layer having a three-layer structure is manufactured, three-stage etching is performed. In the first etching process, an etching method in which the etching rates for the second film and the third film are high is employed, and the first etching process is performed until the first film is at least exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. In the third etching process, an etching method in which the etching rates for the first to the third films are higher than those in the second etching process is preferably employed.

摘要翻译： 当制造包括具有三层结构的导电层的晶体管时，进行三级蚀刻。 在第一蚀刻工艺中，采用其中第二膜和第三膜的蚀刻速率高的蚀刻方法，并且执行第一蚀刻处理直到第一膜至少暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 在第三蚀刻工艺中，优选使用其中第一至第三膜的蚀刻速率高于第二蚀刻工艺中的蚀刻速率的蚀刻方法。

公开(公告)号：US20120299003A1

公开(公告)日：2012-11-29

申请号：US13568186

申请日：2012-08-07

申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Atsushi HIROSE ,  Masashi TSUBUKU ,  Kosei NODA

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Atsushi HIROSE ,  Masashi TSUBUKU ,  Kosei NODA

IPC分类号： H01L29/22 ,  H01L27/15 ,  H01L29/786

CPC分类号： H01L27/1225 ,  H01L21/823412 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/156 ,  H01L27/3213 ,  H01L29/24 ,  H01L29/36 ,  H01L29/7869 ,  H01L29/78693 ,  H01L33/025 ,  H01L2924/0002 ,  H04M1/0266 ,  H04R1/02 ,  H01L2924/00

摘要： An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

摘要翻译： 目的是获得使用其中使用氧化物半导体层的薄膜晶体管，在检测信号和宽动态范围中具有高灵敏度的半导体器件。 使用具有作为沟道形成层的功能的氧化物半导体的薄膜晶体管形成模拟电路，其氢浓度为5×1019个原子/ cm3以下，并且在该状态下基本上起绝缘体的作用 其中不产生电场。 因此，可以获得在检测信号中具有高灵敏度和宽动态范围的半导体器件。

公开(公告)号：US20120138922A1

公开(公告)日：2012-06-07

申请号：US13307398

申请日：2011-11-30

申请人： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Hiroki OHARA ,  Tatsuya HONDA ,  Takatsugu OMATA ,  Yusuke NONAKA ,  Masahiro TAKAHASHI ,  Akiharu MIYANAGA

发明人： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Hiroki OHARA ,  Tatsuya HONDA ,  Takatsugu OMATA ,  Yusuke NONAKA ,  Masahiro TAKAHASHI ,  Akiharu MIYANAGA

IPC分类号： H01L29/12

CPC分类号： H01L29/78696 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693

摘要： An oxide semiconductor film which has more stable electric conductivity is provided. Further, a semiconductor device which has stable electric characteristics and high reliability is provided by using the oxide semiconductor film. An oxide semiconductor film includes a crystalline region, and the crystalline region includes a crystal in which an a-b plane is substantially parallel with a surface of the film and a c-axis is substantially perpendicular to the surface of the film; the oxide semiconductor film has stable electric conductivity and is more electrically stable with respect to irradiation with visible light, ultraviolet light, and the like. By using such an oxide semiconductor film for a transistor, a highly reliable semiconductor device having stable electric characteristics can be provided.

摘要翻译： 提供了具有更稳定的导电性的氧化物半导体膜。 此外，通过使用氧化物半导体膜提供具有稳定的电特性和高可靠性的半导体器件。 氧化物半导体膜包括结晶区域，并且结晶区域包括其中a-b平面基本上平行于膜的表面并且c轴基本上垂直于膜的表面的晶体; 氧化物半导体膜具有稳定的导电性，并且相对于可见光，紫外线等的照射而言更加电稳定。 通过使用这种用于晶体管的氧化物半导体膜，可以提供具有稳定电特性的高可靠性半导体器件。

公开(公告)号：US20110318916A1

公开(公告)日：2011-12-29

申请号：US13228486

申请日：2011-09-09

申请人： Kengo AKIMOTO ,  Masashi TSUBUKU

发明人： Kengo AKIMOTO ,  Masashi TSUBUKU

IPC分类号： H01L21/283

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/41733

摘要： An object is to suppress deterioration of element characteristics even when an oxide semiconductor is formed after a gate insulating layer, a source electrode layer, and a drain electrode layer are formed. A gate electrode layer is formed over a substrate. A gate insulating layer is formed over the gate electrode layer. A source electrode layer and a drain electrode layer are formed over the gate insulating layer. Surface treatment is performed on surfaces of the gate insulating layer, the source electrode layer, and the drain electrode layer which are formed over the substrate. After the surface treatment is performed, an oxide semiconductor layer is formed over the gate insulating layer, the source electrode layer, and the drain electrode layer.

摘要翻译： 即使在形成了栅极绝缘层，源极电极层和漏极电极层之后形成氧化物半导体，也是要抑制元件特性的劣化。 在基板上形成栅极电极层。 在栅电极层上形成栅极绝缘层。 源极电极层和漏电极层形成在栅绝缘层上。 在形成在基板上的栅极绝缘层，源极电极层和漏极电极层的表面上进行表面处理。 在进行表面处理之后，在栅极绝缘层，源极电极层和漏极电极层上形成氧化物半导体层。

公开(公告)号：US20110204362A1

公开(公告)日：2011-08-25

申请号：US13026518

申请日：2011-02-14

申请人： Kengo AKIMOTO ,  Ryosuke WATANABE ,  Masashi TSUBUKU ,  Shunpei YAMAZAKI

发明人： Kengo AKIMOTO ,  Ryosuke WATANABE ,  Masashi TSUBUKU ,  Shunpei YAMAZAKI

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618

摘要： It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.

摘要翻译： 本发明的目的是提供一种包括氧化物半导体的半导体器件，其中实现了晶体管的小型化和电场的集中。 栅电极的宽度减小，源电极层和漏电极层之间的间隔缩短。 通过使用栅电极作为掩模以自对准的方式添加稀有气体，可以在氧化物半导体层中提供与沟道形成区域接触的低电阻区域。 因此，即使栅电极的宽度，即栅极配线的线宽小，也能够提供高电位区域的高位置精度，能够实现晶体管的小型化。

公开(公告)号：US20110059575A1

公开(公告)日：2011-03-10

申请号：US12871122

申请日：2010-08-30

申请人： Masashi TSUBUKU ,  Shuhei YOSHITOMI ,  Takahiro TUJI ,  Miyuki HOSOBA ,  Junichiro SAKATA ,  Hiroyuki TOMATSU ,  Masahiko HAYAKAWA

发明人： Masashi TSUBUKU ,  Shuhei YOSHITOMI ,  Takahiro TUJI ,  Miyuki HOSOBA ,  Junichiro SAKATA ,  Hiroyuki TOMATSU ,  Masahiko HAYAKAWA

IPC分类号： H01L21/34

CPC分类号： H01L27/1262 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02595 ,  H01L21/02631 ,  H01L21/02667 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/7869

摘要： It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.

摘要翻译： 本发明的目的是提供一种包括氧化物半导体膜的薄膜晶体管的结构的制造方法，其中形成沟道的阈值电压为正且尽可能接近0V。 形成保护绝缘层以覆盖包括通过第一热处理脱水或脱氢的氧化物半导体层的薄膜晶体管，以及在比第一热处理低的温度下进行第二热处理，其中， 重复多次温度的降低，由此，在不影响通道长度的情况下，包含氧化物半导体层的薄膜晶体管，其中形成沟道的阈值电压为正且尽可能接近0V，可以 制造。

公开(公告)号：US20110024740A1

公开(公告)日：2011-02-03

申请号：US12846572

申请日：2010-07-29

申请人： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA ,  Junichiro SAKATA

发明人： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA ,  Junichiro SAKATA

IPC分类号： H01L29/786 ,  H01L21/44

CPC分类号： H01L29/78696 ,  H01L27/1225 ,  H01L29/7869

摘要： A semiconductor device having a structure which enables sufficient reduction in parasitic capacitance is provided. In addition, the operation speed of thin film transistors in a driver circuit is improved. In a bottom-gate thin film transistor in which an oxide insulating layer is in contact with a channel formation region in an oxide semiconductor layer, a source electrode layer and a drain electrode layer are formed in such a manner that they do not overlap with a gate electrode layer. Thus, the distance between the gate electrode layer and the source electrode layer and between the gate electrode layer and the drain electrode layer are increased; accordingly, parasitic capacitance can be reduced.

摘要翻译： 提供具有能够充分降低寄生电容的结构的半导体器件。 此外，提高了驱动电路中薄膜晶体管的操作速度。 在其中氧化物绝缘层与氧化物半导体层中的沟道形成区域接触的底栅极薄膜晶体管中，以与栅极薄膜晶体管不重叠的方式形成源电极层和漏电极层， 栅电极层。 因此，栅极电极层与源电极层之间以及栅极电极层和漏极电极层之间的距离增加; 因此，可以减小寄生电容。

公开(公告)号：US20120061663A1

公开(公告)日：2012-03-15

申请号：US13226713

申请日：2011-09-07

申请人： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

发明人： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

IPC分类号： H01L29/12 ,  H01L21/34

CPC分类号： H01L29/7869 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/04 ,  H01L29/24 ,  H01L29/78603

摘要： An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al2O3, α-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or α-Fe2O3) is used.

摘要翻译： 本发明的目的是提供一种具有稳定的电气特性和高可靠性的氧化物半导体膜的半导体装置。 通过在绝缘表面上形成厚度为1nm至10nm的第一材料膜（具有六方晶体结构的膜）形成第一和第二材料膜的叠层，并形成具有六方晶系结构的第二材料膜（ 使用第一材料膜作为核的结晶氧化物半导体膜）。 作为第一材料膜，具有纤锌矿晶体结构的材料膜（例如氮化镓或氮化铝）或具有刚玉晶体结构的材料膜（α-Al 2 O 3，α-Ga 2 O 3，In 2 O 3，Ti 2 O 3，V 2 O 3，Cr 2 O 3，或 α-Fe 2 O 3）。