公开(公告)号：US20120061670A1

公开(公告)日：2012-03-15

申请号：US13220736

申请日：2011-08-30

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1262 ,  H01L21/44 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

摘要： Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.

摘要翻译： 描述了一种用于制造半导体器件的方法。 在绝缘膜上形成掩模，并且掩模的尺寸减小。 使用尺寸减小的掩模形成具有突起的绝缘膜，并且使用具有突起的绝缘膜形成沟道长度减小的晶体管。 此外，在制造晶体管时，在与微细突起的顶面重叠的栅极绝缘膜的表面上进行平坦化处理。 因此，晶体管可以高速运转，可提高可靠性。 此外，绝缘膜被加工成具有突起的形状，由此可以以自对准的方式形成源电极和漏电极。

公开(公告)号：US20100283105A1

公开(公告)日：2010-11-11

申请号：US12840442

申请日：2010-07-21

申请人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA

发明人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC分类号： H01L29/786

CPC分类号： H01L29/41733 ,  H01L21/76804 ,  H01L21/76805 ,  H01L23/485 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.

摘要翻译： 提出了可以容易地控制形成接触孔的蚀刻的半导体器件的制造技术。 半导体器件至少包括形成在绝缘表面上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 以及形成在所述第二绝缘层之上的导电层，所述导电层经由至少在所述半导体层和所述第二绝缘层中形成并且部分地暴露所述绝缘表面的开口连接到所述半导体层。 导电层在形成于半导体层的开口的侧面与半导体层电连接。

公开(公告)号：US20110254004A1

公开(公告)日：2011-10-20

申请号：US13168673

申请日：2011-06-24

申请人： Shunpei YAMAZAKI ,  Kazuko IKEDA ,  Shinya SASAGAWA ,  Hideomi SUZAWA

发明人： Shunpei YAMAZAKI ,  Kazuko IKEDA ,  Shinya SASAGAWA ,  Hideomi SUZAWA

IPC分类号： H01L29/04 ,  H01L29/786

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

摘要： A semiconductor device manufactured utilizing an SOI substrate, in which defects due to an end portion of an island-shaped silicon layer are prevented and the reliability is improved, and a manufacturing method thereof. The following are included: an SOI substrate in which an insulating layer and an island-shaped silicon layer are stacked in order over a support substrate; a gate insulating layer provided over one surface and a side surface of the island-shaped silicon layer; and a gate electrode which is provided over the island-shaped silicon layer with the gate insulating layer interposed therebetween. The gate insulating layer is formed such that the dielectric constant in the region which is in contact with the side surface of the island-shaped silicon layer is lower than that over the one surface of the island-shaped silicon layer.

摘要翻译： 利用SOI衬底制造的半导体器件及其制造方法，其中防止了由岛状硅层的端部引起的缺陷并提高了可靠性。 包括以下：SOI基板，其中绝缘层和岛状硅层依次层叠在支撑基板上; 设置在岛状硅层的一个表面和侧面上的栅极绝缘层; 以及栅极电极，其设置在岛状硅层上，栅极绝缘层插入其间。 栅极绝缘层形成为与岛状硅层的侧面接触的区域的介电常数低于岛状硅层的一个表面的介电常数。

公开(公告)号：US20110117698A1

公开(公告)日：2011-05-19

申请号：US13012987

申请日：2011-01-25

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC分类号： H01L21/465

CPC分类号： H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

摘要： An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

摘要翻译： 本发明的目的是建立一种其中使用氧化物半导体的半导体器件的制造中的加工技术。 在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成氧化物半导体层，通过湿蚀刻加工氧化物半导体层，形成岛状氧化物半导体层 形成导电层以覆盖岛状氧化物半导体层，通过干蚀刻处理导电层以形成源电极，并且通过干蚀刻除去漏电极和岛状氧化物半导体层的一部分， 在岛状氧化物半导体层中形成凹部。

公开(公告)号：US20100105162A1

公开(公告)日：2010-04-29

申请号：US12582074

申请日：2009-10-20

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC分类号： H01L21/336 ,  H01L21/34

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/7869

摘要： In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. The etching step is performed by dry etching in which an etching gas is used.

摘要翻译： 在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜 光透过该掩模以具有多个强度。 蚀刻步骤通过使用蚀刻气体的干蚀刻进行。

公开(公告)号：US20100099216A1

公开(公告)日：2010-04-22

申请号：US12580512

申请日：2009-10-16

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC分类号： H01L21/336

CPC分类号： H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

摘要： An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

摘要翻译： 本发明的目的是建立一种其中使用氧化物半导体的半导体器件的制造中的加工技术。 在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成氧化物半导体层，通过湿蚀刻加工氧化物半导体层，形成岛状氧化物半导体层 形成导电层以覆盖岛状氧化物半导体层，通过干蚀刻处理导电层以形成源电极，并且通过干蚀刻除去漏电极和岛状氧化物半导体层的一部分， 在岛状氧化物半导体层中形成凹部。

公开(公告)号：US20090239354A1

公开(公告)日：2009-09-24

申请号：US12399047

申请日：2009-03-06

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

摘要翻译： 在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层， 通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层， 所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理， 具有激光的晶体半导体层。

公开(公告)号：US20120286266A1

公开(公告)日：2012-11-15

申请号：US13555579

申请日：2012-07-23

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Shunichi ITO ,  Miyuki HOSOBA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Shunichi ITO ,  Miyuki HOSOBA

IPC分类号： H01L29/26

CPC分类号： H01L29/66969 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66742 ,  H01L29/78621 ,  H01L29/7869

摘要： An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.

摘要翻译： 本发明的目的是以低成本，高生产率制造包括氧化物半导体的半导体器件，使得通过减少曝光掩模的数量来简化光刻工艺。在包括通道蚀刻的半导体器件的制造方法中 倒置交错薄膜晶体管，氧化物半导体膜和导电膜使用掩模层进行蚀刻，该掩模层使用作为透光的多色调掩模形成，该透光掩模通过该曝光掩模透射，以便具有多个 强度 在蚀刻步骤中，通过使用蚀刻剂的湿式蚀刻进行第一蚀刻步骤，并且通过使用蚀刻气体的干法蚀刻进行第二蚀刻步骤。

公开(公告)号：US20120187397A1

公开(公告)日：2012-07-26

申请号：US13356012

申请日：2012-01-23

申请人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

发明人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

IPC分类号： H01L29/786

CPC分类号： H01L29/66969 ,  H01L21/02488 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/7869

摘要： A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.

摘要翻译： 提供了包括氧化物半导体并且具有良好的电特性的半导体器件。 在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。 氧化物半导体膜的侧面与绝缘膜接触。 氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。 栅极绝缘膜与氧化物半导体膜形成并接触。 在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。 源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。

公开(公告)号：US20110250723A1

公开(公告)日：2011-10-13

申请号：US13078020

申请日：2011-04-01

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA

IPC分类号： H01L21/336

CPC分类号： H01L29/78636 ,  G11C16/0433 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/7869

摘要： In an embodiment, an insulating film is formed over a flat surface; a mask is formed over the insulating film; a slimming process is performed on the mask; an etching process is performed on the insulating film using the mask; a conductive film covering the insulating film is formed; a polishing process is performed on the conductive film and the insulating film, so that the conductive film and the insulating film have equal thicknesses; the conductive film is etched, so that a source electrode and a drain electrode which are thinner than the conductive film are formed; an oxide semiconductor film is formed in contact with the insulating film, the source electrode, and the drain electrode; a gate insulating film covering the oxide semiconductor film is formed; and a gate electrode is formed in a region which is over the gate insulating film and overlaps with the insulating film.

摘要翻译： 在一个实施例中，在平坦表面上形成绝缘膜; 在绝缘膜上形成掩模; 在面罩上进行减肥过程; 使用掩模对绝缘膜进行蚀刻处理; 形成覆盖绝缘膜的导电膜; 对导电膜和绝缘膜进行抛光处理，使得导电膜和绝缘膜具有相等的厚度; 蚀刻导电膜，形成比导电膜薄的源电极和漏电极; 形成与绝缘膜，源电极和漏电极接触的氧化物半导体膜; 形成覆盖氧化物半导体膜的栅极绝缘膜; 并且栅电极形成在栅极绝缘膜上并与绝缘膜重叠的区域中。