公开(公告)号：US08785241B2

公开(公告)日：2014-07-22

申请号：US13174960

申请日：2011-07-01

申请人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Masashi Tsubuku ,  Daigo Shimada

发明人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Masashi Tsubuku ,  Daigo Shimada

IPC分类号： H01L21/44 ,  H01L21/336

CPC分类号： H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

摘要： When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

摘要翻译： 当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。 在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面提供并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。

公开(公告)号：US08637354B2

公开(公告)日：2014-01-28

申请号：US13159804

申请日：2011-06-14

申请人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Masashi Tsubuku ,  Daigo Shimada

发明人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Masashi Tsubuku ,  Daigo Shimada

IPC分类号： H01L21/00 ,  H01L29/04

CPC分类号： H01L29/7869 ,  H01L29/45 ,  H01L29/66969

摘要： When a transistor including a conductive layer having a three-layer structure is manufactured, three-stage etching is performed. In the first etching process, an etching method in which the etching rates for the second film and the third film are high is employed, and the first etching process is performed until the first film is at least exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. In the third etching process, an etching method in which the etching rates for the first to the third films are higher than those in the second etching process is preferably employed.

摘要翻译： 当制造包括具有三层结构的导电层的晶体管时，进行三级蚀刻。 在第一蚀刻工艺中，采用其中第二膜和第三膜的蚀刻速率高的蚀刻方法，并且执行第一蚀刻处理直到第一膜至少暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 在第三蚀刻工艺中，优选使用其中第一至第三膜的蚀刻速率高于第二蚀刻工艺中的蚀刻速率的蚀刻方法。

公开(公告)号：US08597992B2

公开(公告)日：2013-12-03

申请号：US13026520

申请日：2011-02-14

申请人： Shinya Sasagawa ,  Masashi Tsubuku ,  Hitoshi Nakayama ,  Daigo Shimada

发明人： Shinya Sasagawa ,  Masashi Tsubuku ,  Hitoshi Nakayama ,  Daigo Shimada

IPC分类号： H01L21/00

CPC分类号： H01L21/76838 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/66969 ,  H01L29/7869

摘要： A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.

摘要翻译： 晶体管通过以下方法制造：包括：形成第一布线层; 形成第一绝缘膜以覆盖所述第一布线层; 在所述第一绝缘膜上形成半导体层; 在半导体层上形成导电膜; 并且对所述导电膜进行蚀刻的至少两个步骤以形成彼此分离的第二布线层，其中所述两个蚀刻步骤至少包括在导电膜的蚀刻速率为 高于半导体层的蚀刻速率，以及在导电膜和半导体层的蚀刻速率高于第一蚀刻工艺的蚀刻速率的条件下进行的第二蚀刻工艺。

公开(公告)号：US08247308B2

公开(公告)日：2012-08-21

申请号：US12505020

申请日：2009-07-17

申请人： Akihiro Ishizuka ,  Shinya Sasagawa ,  Motomu Kurata ,  Atsushi Hikosaka ,  Taiga Muraoka ,  Hitoshi Nakayama

发明人： Akihiro Ishizuka ,  Shinya Sasagawa ,  Motomu Kurata ,  Atsushi Hikosaka ,  Taiga Muraoka ,  Hitoshi Nakayama

IPC分类号： H01L21/30

CPC分类号： H01L21/76254

摘要： It is an object of the preset invention to increase adhesiveness of a semiconductor layer and a base substrate and to reduce defective bonding. An oxide film is formed on a semiconductor substrate and the semiconductor substrate is irradiated with accelerated ions through the oxide film, whereby an embrittled region is formed at a predetermined depth from a surface of the semiconductor substrate. Plasma treatment is performed on the oxide film on the semiconductor substrate and the base substrate by applying a bias voltage, the surface of the semiconductor substrate and a surface of the base substrate are disposed opposite to each other, a surface of the oxide film is bonded to the surface of the base substrate, heat treatment is performed after the surface of the oxide film is bonded to the surface of the base substrate, and separation is caused along the embrittled region, whereby a semiconductor layer is formed over the base substrate with the oxide film interposed therebetween.

摘要翻译： 本发明的一个目的是增加半导体层和基底衬底的粘附性并减少不良接合。 在半导体衬底上形成氧化物膜，半导体衬底通过氧化膜照射加速离子，从而在半导体衬底的表面形成预定深度的脆化区域。 通过施加偏置电压对半导体衬底和基底衬底上的氧化物膜进行等离子体处理，半导体衬底的表面和基底衬底的表面彼此相对设置，氧化膜的表面被接合 在基底表面上进行热处理之后，在氧化膜的表面接合到基底表面之后进行热处理，沿着脆化区域分离，由此在基底基板上形成半导体层 氧化膜。

公开(公告)号：US09093539B2

公开(公告)日：2015-07-28

申请号：US13466664

申请日：2012-05-08

申请人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Hiroshi Fujiki

发明人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Hiroshi Fujiki

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/36 ,  H01L29/66 ,  H01L27/12 ,  H01L21/02

CPC分类号： H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

摘要： To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.

摘要翻译： 为了建立包括In-Sn-Zn-O类半导体的半导体器件的制造中的加工技术。 通过使用含氯气体如Cl 2，BCl 3，SiCl 4等的干蚀刻来选择性地蚀刻In-Sn-Zn-O系半导体层。 在形成源极电极层和漏电极层时，可以选择性地蚀刻与In-Sn-Zn-O系半导体层接触的导电层，同时很少去除In-Sn-Zn-O系半导体层， 除了含有氯的气体之外，还使用含有氧或氟的气体。

公开(公告)号：US07267839B2

公开(公告)日：2007-09-11

申请号：US10921869

申请日：2004-08-20

申请人： Koji Tanaka ,  Hitoshi Nakayama ,  Shinji Atsuzawa ,  Youichi Andoh

发明人： Koji Tanaka ,  Hitoshi Nakayama ,  Shinji Atsuzawa ,  Youichi Andoh

IPC分类号： B05D1/26

CPC分类号： B05B15/68

摘要： Disclosed is a method, in which when a liquid material is applied to the application surface of an object of application by using a liquid material supply device having a syringe containing the liquid material and equipped with a needle having at its distal end an ejection hole from which the liquid material is ejected, an image of the distal end of the needle is taken laterally by a horizontal camera together with a height reference mark when an ascent/descent drive system of the liquid material supply device is set to a reference height, and the height position of the distal end of the needle is obtained from the difference between the height of the distal end of the needle and the height of the height reference mark.

摘要翻译： 公开了一种方法，其中当通过使用具有含有液体材料的注射器的液体材料供应装置将液体材料施加到施加物体的施加表面上并且配备有在其远端具有喷射孔的喷射孔时， 当液体材料供给装置的上升/下降驱动系统被设定为参考高度时，液体材料被喷射的情况下，水平摄像机的横向摄像机与高度参考标记一起被拍摄针的远端的图像，以及 针的远端的高度位置是根据针的远端的高度与高度参考标记的高度之间的差来获得的。

公开(公告)号：US5878484A

公开(公告)日：1999-03-09

申请号：US631827

申请日：1995-12-28

申请人： Shinichi Araya ,  Kouji Kudou ,  Akihiro Katou ,  Hitoshi Nakayama ,  Masakazu Toki ,  Kazuya Abe

发明人： Shinichi Araya ,  Kouji Kudou ,  Akihiro Katou ,  Hitoshi Nakayama ,  Masakazu Toki ,  Kazuya Abe

IPC分类号： H05K13/04 ,  H05K3/30

CPC分类号： H05K13/0413 ,  Y10T29/49131 ,  Y10T29/53091 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53191

摘要： A chip mounting apparatus capable of permitting a chip mounting operation to be executed at an increased speed and ensuring continuous running of the apparatus over a long period of time. The apparatus includes a chip observing camera mounted on the side of a chip mounting head, a lighting unit mounted on the side of the chip mounting head to light a background of a chip held on a chip suction nozzle of the head, a reflection unit mounted on the side of the chip mounting head to input an image of the chip to the chip observing camera, feeder and stocker sections each adapted to replaceably held a chip storage package therein, and a package replacement mechanism for carrying out replacement of the chip storage package between both sections.

摘要翻译： 一种芯片安装装置，其能够以更高的速度进行芯片安装操作，并且确保设备在长时间内的连续运行。 该装置包括安装在芯片安装头侧的芯片观察摄像机，安装在芯片安装头侧的照明单元，以照亮保持在头部的芯片吸嘴上的芯片的背景;安装 在芯片安装头的侧面，将芯片的图像输入到芯片观察摄像机，馈送器和储片器部分，每个适配器可更换地保持其中的芯片存储包装;以及封装更换机构，用于执行芯片存储封装 两部分之间。

公开(公告)号：US5296635A

公开(公告)日：1994-03-22

申请号：US975952

申请日：1992-11-13

申请人： Motohiro Kase ,  Hitoshi Nakayama ,  Masaru Wada ,  Teruyuki Nagata ,  Akihiro Yamaguchi

发明人： Motohiro Kase ,  Hitoshi Nakayama ,  Masaru Wada ,  Teruyuki Nagata ,  Akihiro Yamaguchi

IPC分类号： C07C201/12 ,  C07C205/38 ,  C07C315/04 ,  C07C317/22 ,  C07C319/20 ,  C07C323/20 ,  C07C41/09 ,  C07C205/06

CPC分类号： C07C201/12 ,  C07C315/04 ,  C07C319/20

摘要： A preparation process of a bis(3-nitrophenoxy) compound represented by the formula: ##STR1## wherein X is a direct bond, divalent hydrocarbon having from 1 to 10 carbon atoms or a divalent group selected from --C(CF.sub.3).sub.2, --CO--, --S--, --SO--, SO.sub.2 --or --O--, which comprises reacting 4,4'-bisphenol with m-dinitrobenzene in the presence of an alkali metal carbonate or alkali metal hydrogen carbonate having a particle size of 250 .mu.m or less while removing generated water from the reaction system during the reaction. In one embodiment of the process, the reaction is carried out while simultaneously adding 4,4'-bisphenol and m-dinitrobenzene to a reaction vessel which was previously charged with the base and an aprotic polar solvent.

摘要翻译： 由下式表示的双（3-硝基苯氧基）化合物的制备方法：其中X是直接键，具有1至10个碳原子的二价烃或选自-C（CF 3）2 - 的二价基团， CO-，-S-，-SO-，SO 2 - 或-O-，其包括在碱金属碳酸盐或粒度为250的碱金属碳酸氢盐存在下使4,4'-双酚与间二硝基苯反应 在反应期间从反应体系中除去产生的水。 在该方法的一个实施方案中，反应进行同时向预先装入碱和反质子极性溶剂的反应容器中加入4,4'-双酚和间二硝基苯。

公开(公告)号：US4827891A

公开(公告)日：1989-05-09

申请号：US82345

申请日：1987-08-06

申请人： Nobuo Miura ,  Hitoshi Nakayama ,  Nolihisa Ishii ,  Hidenori Maeda

发明人： Nobuo Miura ,  Hitoshi Nakayama ,  Nolihisa Ishii ,  Hidenori Maeda

IPC分类号： F02P3/09

CPC分类号： F02P3/093

摘要： An ignition apparatus of a capacitor discharge ignition type comprises: an ignition timing signal generator to generate an ignition timing signal synchronized with the rotation of the engine; a capacitor; a blocking oscillator; a rectifier for rectifying the output voltage of the blocking oscillator and applying the rectified voltage to the capacitor thereby charging the capacitor; a switching device which is turned on in response to the ignition timing signal and discharges the stored charges of the capacitor, thereby generating a pulse voltage across the terminals of the primary winding of an ignition coil; and an ignition plug to generate a spark discharge by a high voltage generated in the secondary winding of the ignition coil. The blocking oscillator oscillates concurrently with the engine rotation. When the ignition timing signal is generated, the oscillation of the blocking oscillator is stopped in accordance with a phase of the output voltage of the AC generator. With this apparatus, a vain charging of the capacitor and a vain spark discharge can be prevented when the engine's rotation stops. The generation of a counter torque on the engine can be certainly prevented.

摘要翻译： 电容放电点火型点火装置包括：点火定时信号发生器，用于产生与发动机旋转同步的点火正时信号; 电容器 阻塞振荡器; 整流器，用于整流阻塞振荡器的输出电压，并将整流电压施加到电容器，从而对电容器充电; 开关装置，其响应于点火正时信号而导通，并且释放所存储的电容器的电荷，从而在点火线圈的初级绕组的端子两端产生脉冲电压; 以及火花塞，通过在点火线圈的次级绕组中产生的高电压产生火花放电。 阻塞振荡器与发动机旋转同时振荡。 当产生点火定时信号时，根据交流发电机的输出电压的相位停止阻塞振荡器的振荡。 利用该装置，当发动机的转动停止时，可以防止电容器的充电和无效的火花放电。 可以可靠地防止在发动机上产生反扭矩。

公开(公告)号：US4719896A

公开(公告)日：1988-01-19

申请号：US2969

申请日：1987-01-13

申请人： Hitoshi Nakayama ,  Nobuo Miura ,  Yoshio Morita ,  Masami Kawabe

发明人： Hitoshi Nakayama ,  Nobuo Miura ,  Yoshio Morita ,  Masami Kawabe

IPC分类号： F02P3/08 ,  F02P3/09

CPC分类号： F02P3/0884

摘要： A capacitive discharge ignition system has first and second bypass elements. The bypass elements are controlled to effect equal charging from the positive and negative portions of the generator alternating power output, and to provide conductive paths for the ignition current outside the generator winding. This lessens current-induced generation of heat in the generator winding.

摘要翻译： 电容放电点火系统具有第一和第二旁路元件。 旁路元件被控制以从发电机交流功率输出的正和负部分实现相等的充电，并且为发电机绕组外部的点火电流提供导电路径。 这减少了发电机绕组中电流产生的热量。