公开(公告)号：US08785241B2

公开(公告)日：2014-07-22

申请号：US13174960

申请日：2011-07-01

申请人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Masashi Tsubuku ,  Daigo Shimada

发明人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Masashi Tsubuku ,  Daigo Shimada

IPC分类号： H01L21/44 ,  H01L21/336

CPC分类号： H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

摘要： When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

摘要翻译： 当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。 在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面提供并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。

公开(公告)号：US08637354B2

公开(公告)日：2014-01-28

申请号：US13159804

申请日：2011-06-14

申请人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Masashi Tsubuku ,  Daigo Shimada

发明人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Masashi Tsubuku ,  Daigo Shimada

IPC分类号： H01L21/00 ,  H01L29/04

CPC分类号： H01L29/7869 ,  H01L29/45 ,  H01L29/66969

摘要： When a transistor including a conductive layer having a three-layer structure is manufactured, three-stage etching is performed. In the first etching process, an etching method in which the etching rates for the second film and the third film are high is employed, and the first etching process is performed until the first film is at least exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. In the third etching process, an etching method in which the etching rates for the first to the third films are higher than those in the second etching process is preferably employed.

摘要翻译： 当制造包括具有三层结构的导电层的晶体管时，进行三级蚀刻。 在第一蚀刻工艺中，采用其中第二膜和第三膜的蚀刻速率高的蚀刻方法，并且执行第一蚀刻处理直到第一膜至少暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 在第三蚀刻工艺中，优选使用其中第一至第三膜的蚀刻速率高于第二蚀刻工艺中的蚀刻速率的蚀刻方法。

公开(公告)号：US08597992B2

公开(公告)日：2013-12-03

申请号：US13026520

申请日：2011-02-14

申请人： Shinya Sasagawa ,  Masashi Tsubuku ,  Hitoshi Nakayama ,  Daigo Shimada

发明人： Shinya Sasagawa ,  Masashi Tsubuku ,  Hitoshi Nakayama ,  Daigo Shimada

IPC分类号： H01L21/00

CPC分类号： H01L21/76838 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/66969 ,  H01L29/7869

摘要： A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.

摘要翻译： 晶体管通过以下方法制造：包括：形成第一布线层; 形成第一绝缘膜以覆盖所述第一布线层; 在所述第一绝缘膜上形成半导体层; 在半导体层上形成导电膜; 并且对所述导电膜进行蚀刻的至少两个步骤以形成彼此分离的第二布线层，其中所述两个蚀刻步骤至少包括在导电膜的蚀刻速率为 高于半导体层的蚀刻速率，以及在导电膜和半导体层的蚀刻速率高于第一蚀刻工艺的蚀刻速率的条件下进行的第二蚀刻工艺。

公开(公告)号：US09093539B2

公开(公告)日：2015-07-28

申请号：US13466664

申请日：2012-05-08

申请人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Hiroshi Fujiki

发明人： Shinya Sasagawa ,  Hitoshi Nakayama ,  Hiroshi Fujiki

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/36 ,  H01L29/66 ,  H01L27/12 ,  H01L21/02

CPC分类号： H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

摘要： To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.

摘要翻译： 为了建立包括In-Sn-Zn-O类半导体的半导体器件的制造中的加工技术。 通过使用含氯气体如Cl 2，BCl 3，SiCl 4等的干蚀刻来选择性地蚀刻In-Sn-Zn-O系半导体层。 在形成源极电极层和漏电极层时，可以选择性地蚀刻与In-Sn-Zn-O系半导体层接触的导电层，同时很少去除In-Sn-Zn-O系半导体层， 除了含有氯的气体之外，还使用含有氧或氟的气体。

公开(公告)号：US08247308B2

公开(公告)日：2012-08-21

申请号：US12505020

申请日：2009-07-17

申请人： Akihiro Ishizuka ,  Shinya Sasagawa ,  Motomu Kurata ,  Atsushi Hikosaka ,  Taiga Muraoka ,  Hitoshi Nakayama

发明人： Akihiro Ishizuka ,  Shinya Sasagawa ,  Motomu Kurata ,  Atsushi Hikosaka ,  Taiga Muraoka ,  Hitoshi Nakayama

IPC分类号： H01L21/30

CPC分类号： H01L21/76254

摘要： It is an object of the preset invention to increase adhesiveness of a semiconductor layer and a base substrate and to reduce defective bonding. An oxide film is formed on a semiconductor substrate and the semiconductor substrate is irradiated with accelerated ions through the oxide film, whereby an embrittled region is formed at a predetermined depth from a surface of the semiconductor substrate. Plasma treatment is performed on the oxide film on the semiconductor substrate and the base substrate by applying a bias voltage, the surface of the semiconductor substrate and a surface of the base substrate are disposed opposite to each other, a surface of the oxide film is bonded to the surface of the base substrate, heat treatment is performed after the surface of the oxide film is bonded to the surface of the base substrate, and separation is caused along the embrittled region, whereby a semiconductor layer is formed over the base substrate with the oxide film interposed therebetween.

摘要翻译： 本发明的一个目的是增加半导体层和基底衬底的粘附性并减少不良接合。 在半导体衬底上形成氧化物膜，半导体衬底通过氧化膜照射加速离子，从而在半导体衬底的表面形成预定深度的脆化区域。 通过施加偏置电压对半导体衬底和基底衬底上的氧化物膜进行等离子体处理，半导体衬底的表面和基底衬底的表面彼此相对设置，氧化膜的表面被接合 在基底表面上进行热处理之后，在氧化膜的表面接合到基底表面之后进行热处理，沿着脆化区域分离，由此在基底基板上形成半导体层 氧化膜。

公开(公告)号：US08436403B2

公开(公告)日：2013-05-07

申请号：US13014081

申请日：2011-01-26

申请人： Shunpei Yamazaki ,  Hiromichi Godo ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata ,  Mayumi Mikami

发明人： Shunpei Yamazaki ,  Hiromichi Godo ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Motomu Kurata ,  Mayumi Mikami

IPC分类号： H01L21/84

CPC分类号： H01L29/7869 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  Y10T428/24421

摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.

摘要翻译： 一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。 源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。 侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

公开(公告)号：US08349671B2

公开(公告)日：2013-01-08

申请号：US12230048

申请日：2008-08-22

申请人： Hidekazu Miyairi ,  Shinya Sasagawa ,  Akihiro Ishizuka

发明人： Hidekazu Miyairi ,  Shinya Sasagawa ,  Akihiro Ishizuka

IPC分类号： H01L21/336

CPC分类号： H01L29/6675 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696 ,  H01L33/0058 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

公开(公告)号：US08236635B2

公开(公告)日：2012-08-07

申请号：US12582074

申请日：2009-10-20

申请人： Hideomi Suzawa ,  Shinya Sasagawa ,  Taiga Muraoka

发明人： Hideomi Suzawa ,  Shinya Sasagawa ,  Taiga Muraoka

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/20

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/7869

摘要： In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. The etching step is performed by dry etching in which an etching gas is used.

摘要翻译： 在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜 光透过该掩模以具有多个强度。 蚀刻步骤通过使用蚀刻气体的干蚀刻进行。

公开(公告)号：US08207025B2

公开(公告)日：2012-06-26

申请号：US13078020

申请日：2011-04-01

申请人： Hideomi Suzawa ,  Shinya Sasagawa

发明人： Hideomi Suzawa ,  Shinya Sasagawa

IPC分类号： H01L21/336

CPC分类号： H01L29/78636 ,  G11C16/0433 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/7869

摘要： In an embodiment, an insulating film is formed over a flat surface; a mask is formed over the insulating film; a slimming process is performed on the mask; an etching process is performed on the insulating film using the mask; a conductive film covering the insulating film is formed; a polishing process is performed on the conductive film and the insulating film, so that the conductive film and the insulating film have equal thicknesses; the conductive film is etched, so that a source electrode and a drain electrode which are thinner than the conductive film are formed; an oxide semiconductor film is formed in contact with the insulating film, the source electrode, and the drain electrode; a gate insulating film covering the oxide semiconductor film is formed; and a gate electrode is formed in a region which is over the gate insulating film and overlaps with the insulating film.

摘要翻译： 在一个实施例中，在平坦表面上形成绝缘膜; 在绝缘膜上形成掩模; 在面罩上进行减肥过程; 使用掩模对绝缘膜进行蚀刻处理; 形成覆盖绝缘膜的导电膜; 对导电膜和绝缘膜进行抛光处理，使得导电膜和绝缘膜具有相等的厚度; 蚀刻导电膜，形成比导电膜薄的源电极和漏电极; 形成与绝缘膜，源电极和漏电极接触的氧化物半导体膜; 形成覆盖氧化物半导体膜的栅极绝缘膜; 并且栅电极形成在栅极绝缘膜上并与绝缘膜重叠的区域中。

公开(公告)号：US07998801B2

公开(公告)日：2011-08-16

申请号：US12424563

申请日：2009-04-16

申请人： Shinya Sasagawa ,  Motomu Kurata ,  Sho Osada

发明人： Shinya Sasagawa ,  Motomu Kurata ,  Sho Osada

IPC分类号： H01L21/00 ,  H01L21/302

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/40 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： Decrease of the off-state current, increase of the on-state current, and reduction of variations of electrical characteristics. A method for manufacturing a channel-etched inversed staggered thin film transistor includes the following steps: removing, by first dry-etching, a part of a semiconductor layer including an impurity element which imparts one conductivity type, which is exposed from the source and drain electrodes, and partially a part of an amorphous semiconductor layer just below and in contact with the part of the semiconductor layer; removing, by second dry-etching, partially the part of the amorphous semiconductor layer which is exposed by the first dry-etching; and performing plasma treatment on the surface of the part of the amorphous semiconductor layer which is exposed by the second dry-etching so that an altered layer is formed.

摘要翻译： 关闭状态电流的减小，导通电流的增加以及电特性变化的减小。 用于制造通道蚀刻反向交错薄膜晶体管的方法包括以下步骤：通过首先干蚀刻除去包括从源极和漏极暴露的赋予一种导电类型的杂质元素的半导体层的一部分 电极，以及半导体层的正下方并与半导体层的一部分接触的部分非晶半导体层的一部分; 通过第二干法蚀刻部分地除去通过第一干法蚀刻暴露的部分非晶半导体层; 并且通过第二干蚀刻曝光的非晶半导体层的部分的表面进行等离子体处理，从而形成改变的层。