公开(公告)号：US5699064A

公开(公告)日：1997-12-16

申请号：US509665

申请日：1995-07-31

申请人： Shiro Sakiyama ,  Shiro Dosho ,  Masakatsu Maruyama ,  George Hayashi ,  Seizo Inagaki ,  Akira Matsuzawa

发明人： Shiro Sakiyama ,  Shiro Dosho ,  Masakatsu Maruyama ,  George Hayashi ,  Seizo Inagaki ,  Akira Matsuzawa

IPC分类号： H03M3/04 ,  H03M1/78

CPC分类号： H03M3/376 ,  H03M3/50

摘要： In an interpolative modulator, a signal which varies by only .+-.1 with one clock from a 1-bit quantizer is used as a shift-direction control signal. The shift-direction control signal is given to a bidirectional shift register. The bidirectional shift register shifts data based on the value of the shift-direction control signal that has been received. The output from the bidirectional shift register is given as a control signal to a resistive-ladder-type D/A converter. The resistive-ladder-type D/A converter outputs an analog potential corresponding to a switch selected by the above control signal. Therefore, if a delay difference occurs between any two bits, two adjacent switches are simply selected simultaneously, so that the output from the resistive-ladder-type D/A converter varies continuously. Consequently, there can be provided an oversampling D/A converter of resistive-ladder type with high accuracy and an increased yield, which is free from glitch (transiently generated noise).

摘要翻译： 在内插调制器中，使用从1比特量化器的一个时钟仅变化+/- 1的信号作为移位方向控制信号。 移位方向控制信号被提供给双向移位寄存器。 双向移位寄存器基于接收到的移位方向控制信号的值来移位数据。 来自双向移位寄存器的输出作为电阻梯型D / A转换器的控制信号给出。 电阻梯型D / A转换器输出与由上述控制信号选择的开关相对应的模拟电位。 因此，如果任意两位之间发生延迟差，则两个相邻的开关被简单地同时选择，使得电阻梯型D / A转换器的输出连续变化。 因此，可以提供具有高精度和增加的产量的电梯梯型的过采样D / A转换器，其没有毛刺（瞬时产生的噪声）。

公开(公告)号：US5550544A

公开(公告)日：1996-08-27

申请号：US200493

申请日：1994-02-23

申请人： Shiro Sakiyama ,  Shiro Dosho ,  Masakatsu Maruyama ,  Hiroyuki Nakahira ,  Toshiyuki Shono ,  Akira Matsuzawa

发明人： Shiro Sakiyama ,  Shiro Dosho ,  Masakatsu Maruyama ,  Hiroyuki Nakahira ,  Toshiyuki Shono ,  Akira Matsuzawa

IPC分类号： H03M3/00 ,  H03M1/00

CPC分类号： H03M3/424 ,  H03M3/456

摘要： The present invention provides a first-order delta-sigma AD converter adapted to conduct noise shaping and having a quantizer arranged such that, when the amplitude of an input signal entered into the quantizer is small, the amplitude of a difference signal between the input signal entered into the quantizer and an output signal therefrom, is small. It is therefore possible to achieve an efficient AD- or DA-converter reduced in power consumption, which satisfies the transmission characteristics of the specifications of CCITT G.714 based on a method of PCM-encoding an audio frequency band signal stipulated in the specifications of CCITT G.711.

摘要翻译： 本发明提供了一种适用于进行噪声整形并具有量化器的一级Δ-ΣAD转换器，其被布置为使得当输入到量化器的输入信号的幅度较小时，输入信号之间的差信号的幅度 进入量化器并且其输出信号很小。 因此，可以实现功率消耗降低的有效的AD转换器或DA转换器，该功率消耗满足CCITT G.714的规格的传输特性，该方法基于对编码 CCITT G.711。

公开(公告)号：US5751142A

公开(公告)日：1998-05-12

申请号：US795906

申请日：1997-03-04

申请人： Shiro Dosho ,  Shiro Sakiyama ,  Masakatsu Maruyama ,  Masatoshi Matsushita ,  Koji Mochizuki

发明人： Shiro Dosho ,  Shiro Sakiyama ,  Masakatsu Maruyama ,  Masatoshi Matsushita ,  Koji Mochizuki

IPC分类号： G05F3/24 ,  G05F3/26 ,  G05F3/20

CPC分类号： G05F3/247 ,  G05F3/262 ,  Y10S323/901

摘要： A reference voltage output terminal of first and second reference voltage generating circuits is connected to a first current input terminal of a current mirror circuit of an operational amplifier by a diode element. At the time of start-up, a reference voltage generated on the reference voltage output terminal is 0 V. Consequently, a current flows to the diode element and an offset voltage Voff is generated on the operational amplifier so that a malfunction point is caused to disappear. Accordingly, in the case where a normal operation point on which a reference voltage having an expected value is generated and a malfunction point on which an operation is stabilized with a reference voltage having a value less than the expected value are present, the generated reference voltage is raised at the time of start-up, passes through the malfunction point to reach an expected voltage value on the normal operation point and becomes stabilized. In this state, the diode element is cut off so that the offset voltage Voff is caused to disappear.

摘要翻译： 第一和第二参考电压产生电路的参考电压输出端通过二极管元件连接到运算放大器的电流镜电路的第一电流输入端。 在启动时，在基准电压输出端子上产生的基准电压为0V。因​​此，电流流向二极管元件，并在运算放大器上产生偏移电压Voff，使得产生故障点 消失。 因此，在存在具有预期值的基准电压的正常工作点和存在具有小于预期值的参考电压使运行稳定的故障点的情况下，产生的基准电压 在启动时升高，通过故障点达到正常工作点的预期电压值并稳定。 在这种状态下，二极管元件被切断，使偏移电压Voff消失。

公开(公告)号：US06424184B1

公开(公告)日：2002-07-23

申请号：US09269315

申请日：1999-03-24

申请人： Akira Yamamoto ,  Shiro Sakiyama ,  Hiroyuki Nakahira ,  Masaru Fukuda ,  Akira Matsuzawa ,  Shiro Dosho ,  Shinichi Yamamoto

发明人： Akira Yamamoto ,  Shiro Sakiyama ,  Hiroyuki Nakahira ,  Masaru Fukuda ,  Akira Matsuzawa ,  Shiro Dosho ,  Shinichi Yamamoto

IPC分类号： H03D300

CPC分类号： G01R23/06 ,  G06F1/3203 ,  Y02D10/126

摘要： A frequency-voltage conversion circuit 21 receives a clock CLK as an input and provides a voltage IVdd in accordance with the frequency of the clock as an output. The input and output characteristic of the frequency-voltage conversion circuit 21 is adjusted to substantially match a given input and output characteristic.

摘要翻译： 频率电压转换电路21接收时钟CLK作为输入，并根据时钟的频率提供电压IVdd作为输出。 频率电压转换电路21的输入和输出特性被调节以基本匹配给定的输入和输出特性。

公开(公告)号：US07808295B2

公开(公告)日：2010-10-05

申请号：US12296021

申请日：2007-06-15

申请人： Shiro Sakiyama ,  Akinori Matsumoto ,  Takashi Morie ,  Shiro Dosho ,  Yusuke Tokunaga

发明人： Shiro Sakiyama ,  Akinori Matsumoto ,  Takashi Morie ,  Shiro Dosho ,  Yusuke Tokunaga

IPC分类号： H03L5/00 ,  H03F3/66

CPC分类号： H03K19/01855 ,  H03K3/0315 ,  H03K3/354

摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°

摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。 给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号 包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

公开(公告)号：US20090134931A1

公开(公告)日：2009-05-28

申请号：US12296021

申请日：2007-06-15

申请人： Shiro Sakiyama ,  Akinori Matsumoto ,  Takashi Morie ,  Shiro Dosho ,  Yusuke Tokunaga

发明人： Shiro Sakiyama ,  Akinori Matsumoto ,  Takashi Morie ,  Shiro Dosho ,  Yusuke Tokunaga

IPC分类号： H03L5/00

CPC分类号： H03K19/01855 ,  H03K3/0315 ,  H03K3/354

摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°

摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。 给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号 包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

公开(公告)号：US07920002B2

公开(公告)日：2011-04-05

申请号：US12133901

申请日：2008-06-05

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

IPC分类号： H03K5/01

CPC分类号： H03K5/00006 ,  H03K5/13

摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

公开(公告)号：US07876166B2

公开(公告)日：2011-01-25

申请号：US12831715

申请日：2010-07-07

申请人： Shiro Dosho ,  Shiro Sakiyama ,  Noriaki Takeda

发明人： Shiro Dosho ,  Shiro Sakiyama ,  Noriaki Takeda

IPC分类号： H03K3/03

CPC分类号： H03K3/0315

摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

摘要翻译： 耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中m×n个相位耦合电路（30） 点在某一相位模式下，相互连接形成一个回路。 逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

公开(公告)号：US07633421B2

公开(公告)日：2009-12-15

申请号：US12093252

申请日：2007-07-30

申请人： Shiro Dosho ,  Takashi Morie ,  Yusuke Tokunaga ,  Shiro Sakiyama

发明人： Shiro Dosho ,  Takashi Morie ,  Yusuke Tokunaga ,  Shiro Sakiyama

IPC分类号： H03M1/12

CPC分类号： H03M1/123 ,  H03M1/1215 ,  H03M1/56

摘要： An A/D converter includes: a plurality of A/D conversion circuits (10 a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.

摘要翻译： A / D转换器包括：多个A / D转换电路（10a，10b）; 输入选择部分（20），用于选择不执行A / D转换的A / D转换电路以提供通过采样保持输入信号获得的模拟量; 以及用于选择不执行A / D转换的A / D转换电路以输出从所选择的数字量获得的数字量的输出选择部分（30）。 每个A / D转换电路包括：用于在多个模拟存储器元件（111）中顺序地存储所提供的模拟量的输入存储器部分（11）。 具有用于将存储在模拟存储器元件中的模拟量转换为数字量的多个A / D转换元件的A / D转换部分（12） 以及移位输出部分（13），具有从A / D转换元件接收数字量以保持数字量的多个寄存器（131），用于移位和输出保存在寄存器中的数字量。

公开(公告)号：US07453313B2

公开(公告)日：2008-11-18

申请号：US11637687

申请日：2006-12-13

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

IPC分类号： G06F3/02

CPC分类号： H02M3/07 ,  H03L7/0895 ,  H03L7/0896

摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.

摘要翻译： 电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。 推挽操作中的另一个用电流镜电路的输出电流进行。