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    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09368185B2

    公开(公告)日：2016-06-14

    申请号：US14508744

    申请日：2014-10-07

    申请人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

    发明人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

    IPC分类号： G11C16/26 ,  G11C11/406

    CPC分类号： G11C11/40615 ,  G11C11/40603 ,  G11C16/26

    摘要： A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.

    摘要翻译： 半导体器件包括多个存储器单元，存取电路，被配置为对存储器单元执行数据读取操作，数据写入操作和数据刷新操作，所述存取电路以选择的第一模式操作 准备执行的第二模式和未准备好执行的第二模式;以及判断电路，被配置为响应于第一命令信息，以使得当访问电路处于第一模式时，访问电路执行数据刷新操作，以及 当访问电路处于第二模式时，访问电路从第二模式退出，然后执行刷新操作。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150098289A1

    公开(公告)日：2015-04-09

    申请号：US14508744

    申请日：2014-10-07

    申请人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

    发明人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

    IPC分类号： G11C11/406

    CPC分类号： G11C11/40615 ,  G11C11/40603 ,  G11C16/26

    摘要： A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.

    摘要翻译： 半导体器件包括多个存储器单元，存取电路，被配置为对存储器单元执行数据读取操作，数据写入操作和数据刷新操作，所述存取电路以选择的第一模式操作 准备执行的第二模式和未准备好执行的第二模式;以及判断电路，被配置为响应于第一命令信息，以使得当访问电路处于第一模式时，访问电路执行数据刷新操作，以及 当访问电路处于第二模式时，访问电路从第二模式退出，然后执行刷新操作。

    Memory module
    6.
    发明授权
    Memory module 有权
    内存模块

    公开(公告)号：US07440289B2

    公开(公告)日：2008-10-21

    申请号：US11987080

    申请日：2007-11-27

    申请人： Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

    发明人： Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

    IPC分类号： H05K7/00

    CPC分类号： H05K1/181 ,  G11C5/00 ,  H05K1/0298 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611

    摘要： A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.

    摘要翻译： 存储器模块包括经由模块基板设置在与存储器缓冲器相对的位置处的存储器芯片MC1，经由模块基板设置在与存储器缓冲器不相对的位置处的存储芯片MC 3和布置在存储器缓冲器 在与存储芯片MC3相对的位置经由模块基板。 连接到存储芯片MC 1的布线部分和连接到存储芯片MC 3和MC 11的布线部分分支的分支点位于从平面安装位置 的存储器缓冲器和存储芯片MC 3和MC 11的平面安装位置。 因此，可以使布线部的布线长度足够短。

    Load reduced memory module
    7.
    发明申请
    Load reduced memory module 审中-公开
    减少内存模块

    公开(公告)号：US20100312956A1

    公开(公告)日：2010-12-09

    申请号：US12801325

    申请日：2010-06-03

    申请人： Atsushi Hiraishi ,  Toshio Sugano ,  Fumiyuki Osanai ,  Masayuki Nakamura ,  Hiroki Fujisawa ,  Shunichi Saito

    发明人： Atsushi Hiraishi ,  Toshio Sugano ,  Fumiyuki Osanai ,  Masayuki Nakamura ,  Hiroki Fujisawa ,  Shunichi Saito

    IPC分类号： G06F12/00 ,  G06F3/00

    CPC分类号： G11C5/04 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.

    摘要翻译： 存储器模块包括多个存储器芯片和安装在模块基板上的多个数据寄存器缓冲器。 至少两个存储器芯片被分配给每个数据寄存器缓冲器。 每个数据寄存器缓冲器包括通过第一数据线连接到数据连接器的M个输入/输出端子（M是等于或大于1的正整数）和N个输入/输出端子（N是正整数等于 大于2M），其经由第二和第三数据线连接到对应的存储器芯片，使得第二和第三数据线的数量是第一数据线的数量的N / M倍。 根据本发明，由于第二和第三数据线的负载容量减少了很多，所以可以实现相当高的数据传输速率。

    Memory module
    8.
    发明申请
    Memory module 有权
    内存模块

    公开(公告)号：US20080123303A1

    公开(公告)日：2008-05-29

    申请号：US11987080

    申请日：2007-11-27

    申请人： Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

    发明人： Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

    IPC分类号： H05K7/00

    CPC分类号： H05K1/181 ,  G11C5/00 ,  H05K1/0298 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611

    摘要： A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.

    摘要翻译： 存储器模块包括经由模块基板设置在与存储器缓冲器相对的位置处的存储器芯片MC1，经由模块基板设置在与存储器缓冲器不相对的位置处的存储芯片MC 3和布置在存储器缓冲器 在与存储芯片MC3相对的位置经由模块基板。 连接到存储芯片MC 1的布线部分和连接到存储芯片MC 3和MC 11的布线部分分支的分支点位于从平面安装位置 的存储器缓冲器和存储芯片MC 3和MC 11的平面安装位置。因此，可以使布线部分的布线长度足够短。