利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.023 秒)

    Manufacturing method of semiconductor device
    1.
    发明授权
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US08501585B2

    公开(公告)日：2013-08-06

    申请号：US12247439

    申请日：2008-10-08

    申请人： Shunpei Yamazaki ,  Takeshi Shichi ,  Naoki Suzuki

    发明人： Shunpei Yamazaki ,  Takeshi Shichi ,  Naoki Suzuki

    IPC分类号： H01L21/30 ,  H01L21/46

    CPC分类号： H01L27/1266 ,  H01L27/1214 ,  H01L29/66772 ,  H01L29/78621

    摘要： To realize high performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type is added to a first semiconductor wafer in order to control the threshold voltage of a transistor included in the semiconductor device, before separating a single crystal semiconductor layer used as a channel formation region of the transistor from the first semiconductor wafer and transferring the single crystal semiconductor layer to a second semiconductor wafer.

    摘要翻译： 通过根据所需功能控制晶体管的电特性来实现半导体器件的高性能和低功耗。 此外，制造这种半导体器件的产率高，生产率高，而不会使制造工艺复杂化。 在将用作晶体管的沟道形成区域的单晶半导体层与第一半导体分离之前，向第一半导体晶片添加赋予一种导电类型的杂质元素，以便控制包括在半导体器件中的晶体管的阈值电压 并将单晶半导体层转移到第二半导体晶片。

    Manufacturing method of semiconductor device
    2.
    发明授权
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US08455331B2

    公开(公告)日：2013-06-04

    申请号：US12246640

    申请日：2008-10-07

    申请人： Shunpei Yamazaki ,  Takeshi Shichi ,  Naoki Suzuki

    发明人： Shunpei Yamazaki ,  Takeshi Shichi ,  Naoki Suzuki

    IPC分类号： H01L21/10 ,  H01L21/46

    CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772

    摘要： To realize high performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type is added to a semiconductor substrate in order to control the threshold voltage of a transistor included in the semiconductor device, before separating a semiconductor layer of the transistor from the semiconductor substrate and transferring the semiconductor layer to a supporting substrate that is a substrate having an insulating surface.

    摘要翻译： 通过根据所需功能控制晶体管的电特性来实现半导体器件的高性能和低功耗。 此外，制造这种半导体器件的产率高，生产率高，而不会使制造工艺复杂化。 在将半导体衬底的半导体层与半导体衬底分离并将半导体层转移到支撑衬底之前，向半导体衬底添加赋予一种导电类型的杂质元素，以便控制包括在半导体器件中的晶体管的阈值电压 即具有绝缘面的基板。

    Method for manufacturing SOI substrate
    3.
    发明授权
    Method for manufacturing SOI substrate 有权

    公开(公告)号：US08629030B2

    公开(公告)日：2014-01-14

    申请号：US13411864

    申请日：2012-03-05

    申请人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

    发明人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

    IPC分类号： H01L21/33 ,  H01L21/8222

    摘要： The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween.

    Thin film transistors and semiconductor device
    5.
    发明授权
    Thin film transistors and semiconductor device 有权
    薄膜晶体管和半导体器件

    公开(公告)号：US07307282B2

    公开(公告)日：2007-12-11

    申请号：US10727651

    申请日：2003-12-05

    申请人： Shunpei Yamazaki ,  Toru Mitsuki ,  Kenji Kasahara ,  Taketomi Asami ,  Tamae Takano ,  Takeshi Shichi ,  Chiho Kokubo ,  Yasuyuki Arai

    发明人： Shunpei Yamazaki ,  Toru Mitsuki ,  Kenji Kasahara ,  Taketomi Asami ,  Tamae Takano ,  Takeshi Shichi ,  Chiho Kokubo ,  Yasuyuki Arai

    IPC分类号： H01L29/04

    CPC分类号： H01L29/66757 ,  H01L29/78684

    摘要： The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.1 atomic % but not larger than 10 atomic % while adding a metal element thereto, wherein not smaller than 20% of the lattice plane {101} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, not larger than 3% of the lattice plane {001} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, and not larger than 5% of the lattice plane {111} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film as detected by the electron backscatter diffraction pattern method.

    摘要翻译： TFT具有通过以以不小于0.1原子％但不大于10原子％的量将含有硅作为主要成分的非晶半导体膜和锗进行热处理和结晶而获得的晶体半导体膜形成的沟道形成区域， 同时向其中添加金属元素，其中不小于晶格面{101}的20％相对于半导体膜的表面具有不大于10度的角度，不大于晶格面{001 }相对于半导体膜的表面具有不大于10度的角度，并且不大于晶格面{111}的5％的角度相对于半导体的表面具有不大于10度的角度 通过电子背散射衍射图法检测。

    Method for manufacturing SOI substrate
    8.
    发明授权
    Method for manufacturing SOI substrate 有权
    制造SOI衬底的方法

    公开(公告)号：US08658508B2

    公开(公告)日：2014-02-25

    申请号：US13411864

    申请日：2012-03-05

    申请人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

    发明人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

    IPC分类号： H01L21/33 ,  H01L21/8222

    CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772

    摘要： The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween.

    摘要翻译： 本发明提供一种制造SOI衬底的方法，即使在非质量分离型离子照射方法为非质子分离型离子照射方法的情况下，通过有利地分离单晶半导体衬底来提高分离后的单晶半导体层的表面的平面性 并且在分离之后提高单晶半导体层的表面的平面性以及提高生产量。 该方法包括以下步骤：当单晶半导体衬底被冷却以在单晶半导体衬底中形成脆化区域时，通过离子掺杂方法照射具有加速离子的单晶半导体衬底; 将单晶半导体衬底和基底衬底之间插入绝缘层; 并且沿着脆化区域分离单晶半导体衬底，以在基底衬底上形成绝缘层，形成单晶半导体层。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06787807B2

    公开(公告)日：2004-09-07

    申请号：US09882265

    申请日：2001-06-18

    申请人： Shunpei Yamazaki ,  Toru Mitsuki ,  Kenji Kasahara ,  Taketomi Asami ,  Tamae Takano ,  Takeshi Shichi ,  Chiho Kokubo

    发明人： Shunpei Yamazaki ,  Toru Mitsuki ,  Kenji Kasahara ,  Taketomi Asami ,  Tamae Takano ,  Takeshi Shichi ,  Chiho Kokubo

    IPC分类号： H01L2904

    CPC分类号： H01L29/78696 ,  G02F1/13454 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/045 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78684

    摘要： The orientation of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film is improved and a TFT formed from this crystalline semiconductor film is provided. In a semiconductor device whose TFT is formed from a semiconductor layer mainly containing silicon, the semiconductor layer has a channel formation region and an impurity region doped with an impurity of one type of conductivity. 20% or more of the channel formation region is the {101} lattice plane that forms an angle of equal to or less than 10 degree with respect to the surface of the crystalline semiconductor film, the plane being detected by an electron backscatter diffraction pattern method, 3% or less of the channel formation region is the {001} lattice plane that forms an angle of equal to or less than 10 degree with respect to the surface of the crystalline semiconductor film, 5% or less of the channel formation region is the {111} lattice plane that forms an angle of equal to or less than 10 degree with respect to the surface of the crystalline semiconductor film.

    摘要翻译： 通过使非晶半导体膜结晶而获得的结晶半导体膜的取向得到改善，并且提供了由该结晶半导体膜形成的TFT。 在其TFT由主要含硅的半导体层形成的半导体器件中，半导体层具有沟道形成区和掺杂有一种导电类型的杂质的杂质区。 沟道形成区域的20％以上是相对于结晶半导体膜的表面形成等于或小于10度的角度的{101}晶格面，通过电子反向散射衍射图法检测的平面 ，3％以下的沟道形成区域相对于结晶半导体膜的表面形成等于或小于10度的{001}晶格面，5％以下的沟道形成区域为 相对于晶体半导体膜的表面形成等于或小于10度的角度的{111}晶格面。