公开(公告)号：US20150162301A1

公开(公告)日：2015-06-11

申请号：US14276320

申请日：2014-05-13

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Huei-Nuan Huang ,  Mu-Hsuan Chan ,  Chun-Tang Lin

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0655 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/92 ,  H01L2224/95 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/10378 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2221/68304 ,  H01L21/56 ,  H01L21/304 ,  H01L2221/68381

Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a carrier having at least a semiconductor chip disposed thereon, the semiconductor chip having a first surface attached to the carrier, and an opposite second surface having a plurality of first conductive elements thereon; disposing an interposer on the first conductive elements, wherein the interposer has opposite third and fourth surfaces, the interposer is disposed on the first conductive elements via the third surface, and a plurality of conductive posts are embedded in the interposer and electrically connected to the third surface; forming an encapsulant on the carrier for encapsulating the semiconductor chip and the interposer; removing a portion of the encapsulant from the upper surface thereof and a portion of the interposer from the fourth surface thereof to expose ends of the conductive posts; and removing the carrier, thereby improving the connection quality between the semiconductor chip and the interposer.

Abstract translation: 提供一种制造半导体封装的方法，其包括以下步骤：提供至少具有其上设置的半导体芯片的载体，所述半导体芯片具有附接到载体的第一表面，以及相对的第二表面，具有多个第一 导电元件; 在所述第一导电元件上设置插入件，其中所述插入件具有相对的第三和第四表面，所述插入件经由所述第三表面设置在所述第一导电元件上，并且多个导电柱嵌入所述插入件中并电连接到所述第三导电元件 表面; 在载体上形成密封剂以封装半导体芯片和插入件; 从其上表面去除所述密封剂的一部分和从所述第四表面移除所述插入件的一部分以暴露所述导电柱的端部; 并移除载体，从而提高半导体芯片和插入件之间的连接质量。

公开(公告)号：US20130326873A1

公开(公告)日：2013-12-12

申请号：US13964488

申请日：2013-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Huei-Nuan Huang ,  Pin-Cheng Huang ,  Chun-Hung Lu ,  Chun-Chieh Chao ,  Chi-Hsin Chiu

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  B82Y30/00 ,  H01L21/486 ,  H01L23/142 ,  H01L23/367 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  Y10T29/49139 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

Abstract: An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity.

Abstract translation: 公开了一种内层散热板和具有内层散热板的多芯片堆叠封装结构。 内层散热板包括形成有多个穿透导电通孔的金属板体，每个穿透导电通孔包括多个纳米线，以及具有填充有纳米线的纳米孔的氧化块。 多芯片堆叠封装结构包括分别设置在内层散热板上的第一芯片和电子部件，从而促进多芯片堆叠结构中的散热以及增加整体封装刚性。