公开(公告)号：US20140118019A1

公开(公告)日：2014-05-01

申请号：US14044122

申请日：2013-10-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Pin-Cheng Huang ,  Yi-Che Lai

IPC: G01R31/26

CPC classification number: G01R1/0408 ,  G01R31/2886 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method of testing a semiconductor structure is provided, including providing at least a semiconductor structure having an interposer and a semiconductor element disposed on the interposer; disposing the semiconductor structure on a carrier having a supporting portion, with the interposer being supported by the supporting portion; and performing a test process. The semiconductor structure has been tested for its electrical performance prior to packaging, thereby eliminating the necessity for a conductive pathway to pass through an inner circuit of an package substrate. Therefore, the testing process is accelerated and the time is save.

Abstract translation: 提供了一种测试半导体结构的方法，包括提供至少一个具有插入件的半导体结构和设置在插入器上的半导体元件; 将半导体结构设置在具有支撑部分的载体上，其中插入件由支撑部分支撑; 并执行测试过程。 半导体结构在封装之前已被测试其电性能，从而消除了导电通路必须通过封装衬底的内部电路。 因此，测试过程加快，节省时间。

公开(公告)号：US20130326873A1

公开(公告)日：2013-12-12

申请号：US13964488

申请日：2013-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Huei-Nuan Huang ,  Pin-Cheng Huang ,  Chun-Hung Lu ,  Chun-Chieh Chao ,  Chi-Hsin Chiu

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  B82Y30/00 ,  H01L21/486 ,  H01L23/142 ,  H01L23/367 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  Y10T29/49139 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

Abstract: An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity.

Abstract translation: 公开了一种内层散热板和具有内层散热板的多芯片堆叠封装结构。 内层散热板包括形成有多个穿透导电通孔的金属板体，每个穿透导电通孔包括多个纳米线，以及具有填充有纳米线的纳米孔的氧化块。 多芯片堆叠封装结构包括分别设置在内层散热板上的第一芯片和电子部件，从而促进多芯片堆叠结构中的散热以及增加整体封装刚性。

公开(公告)号：US09720013B2

公开(公告)日：2017-08-01

申请号：US14044122

申请日：2013-10-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Pin-Cheng Huang ,  Yi-Che Lai

IPC: G01R31/26 ,  G01R1/04 ,  G01R31/28

CPC classification number: G01R1/0408 ,  G01R31/2886 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method of testing a semiconductor structure is provided, including providing at least a semiconductor structure having an interposer and a semiconductor element disposed on the interposer; disposing the semiconductor structure on a carrier having a supporting portion, with the interposer being supported by the supporting portion; and performing a test process. The semiconductor structure has been tested for its electrical performance prior to packaging, thereby eliminating the necessity for a conductive pathway to pass through an inner circuit of an package substrate. Therefore, the testing process is accelerated and the time is save.

公开(公告)号：US20140127838A1

公开(公告)日：2014-05-08

申请号：US13845698

申请日：2013-03-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Pin-Cheng Huang ,  Chun-Tang Lin ,  Wen-Tsung Tseng ,  Yi-Che Lai

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L21/6836 ,  H01L22/20 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16195 ,  H01L2924/351 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.

Abstract translation: 提供了一种测试半导体封装的方法，包括：至少在粘合剂层的顶表面上设置插入件，所述插入件具有第一表面和与第一表面相对的第二表面，多个导电元件设置在第二表面之间 插入器的第二表面和粘合剂层; 在所述插入件的第一表面上设置至少一个半导体芯片，并且经由所述导电元件对所述半导体芯片进行电测试，其中如果存在设置在所述插入件的第一表面上的多个半导体芯片，则所述步骤 重复设置半导体芯片并对半导体芯片进行电气测试; 并去除粘合剂层。 通过使用该方法，半导体封装的制造成本和设备成本降低，产品产量增加。

公开(公告)号：US08987012B2

公开(公告)日：2015-03-24

申请号：US13845698

申请日：2013-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Pin-Cheng Huang ,  Chun-Tang Lin ,  Wen-Tsung Tseng ,  Yi-Che Lai

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L21/6836 ,  H01L22/20 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16195 ,  H01L2924/351 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.

Abstract translation: 提供了一种测试半导体封装的方法，包括：至少在粘合剂层的顶表面上设置插入件，所述插入件具有第一表面和与第一表面相对的第二表面，多个导电元件设置在第二表面之间 插入器的第二表面和粘合剂层; 在所述插入件的第一表面上设置至少一个半导体芯片，并且经由所述导电元件对所述半导体芯片进行电测试，其中如果存在设置在所述插入件的第一表面上的多个半导体芯片，则所述步骤 重复设置半导体芯片并对半导体芯片进行电气测试; 并去除粘合剂层。 通过使用该方法，半导体封装的制造成本和设备成本降低，产品产量增加。