公开(公告)号：US5930890A

公开(公告)日：1999-08-03

申请号：US858192

申请日：1997-04-21

申请人： William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

发明人： William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

IPC分类号： G03F7/26 ,  H01L21/48 ,  H01L23/12 ,  H01L23/52 ,  H05K3/18 ,  H05K3/40 ,  H01K3/10

CPC分类号： H05K3/4007 ,  H01L21/4853 ,  H01L2924/00013 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0577 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

摘要： An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.

摘要翻译： 通过在基板上形成第一层正性光致抗蚀剂，通过在第一层上软化烘烤该第一层并将其暴露在短时间内，用一个整体电路芯片来形成用于安装诸如集成电路芯片的微电子器件的互连柱， 宽孔径面罩或简单的UV空白洪水曝光。 在不显影第一层的情况下，将第二层正性抗蚀剂涂覆在第一层上，软化，然后用窄孔径掩模曝光。 在第二层的软烘烤期间，光致抗蚀剂化合物中的一些活化剂扩散到第一层的暴露部分，并以这样的方式改变其溶解度，使得当这些层随后显影时，显影剂部分地削弱未曝光 第一层的部分以在光致抗蚀剂中形成具有大致均匀横截面的开口。 然后可以通过电镀填充该开口以产生强大的整体互连柱。

公开(公告)号：US5916453A

公开(公告)日：1999-06-29

申请号：US717266

申请日：1996-09-20

申请人： Solomon I. Beilin ,  Michael G. Lee ,  William T. Chou ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

发明人： Solomon I. Beilin ,  Michael G. Lee ,  William T. Chou ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

IPC分类号： H01L21/3105 ,  H01L21/321 ,  H05K3/24 ,  H05K3/46 ,  C25F3/16

CPC分类号： H01L21/31053 ,  H05K3/4647 ,  H05K2203/025 ,  H05K2203/0733 ,  H05K3/243

摘要： Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is then formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

摘要翻译： 公开了在基板和晶片的表面上形成的结构的平面化方法。 所述方法在所述表面和所述结构或所述结构的形成位置上形成平坦化层，使得所述层的顶表面在所述结构的位置之间具有低区域，并且使得所述低区域基本上位于所述结构 在低于结构顶部的平面内。 然后在平坦化层的低区域上形成抛光停止层，抛光停止层比平坦化层更能抵抗抛光，并且优选地，结构。 然后将所得表面抛光。 抛光可以通过例如标准机械抛光和化学机械抛光来实现。

公开(公告)号：US06733685B2

公开(公告)日：2004-05-11

申请号：US09881514

申请日：2001-06-12

申请人： Solomon I. Beilin ,  Michael G. Lee ,  William T. Chou ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

发明人： Solomon I. Beilin ,  Michael G. Lee ,  William T. Chou ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

IPC分类号： B44C122

CPC分类号： H01L21/31053 ,  H05K3/243 ,  H05K3/4647 ,  H05K2203/025 ,  H05K2203/0733

摘要： Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

摘要翻译： 公开了在基板和晶片的表面上形成的结构的平面化方法。 所述方法在所述表面和所述结构或所述结构将被形成的位置上形成平坦化层，使得所述层的顶表面在所述结构的位置之间具有低区域，并且使得所述低区域基本上位于 在低于结构顶部的平面内。 在平坦化层的低面积上形成抛光停止层，抛光停止层比平坦化层更能抵抗抛光，优选结构。 然后将所得表面抛光。 抛光可以通过例如标准机械抛光和化学机械抛光来实现。

公开(公告)号：US5722162A

公开(公告)日：1998-03-03

申请号：US541219

申请日：1995-10-12

申请人： William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

发明人： William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

IPC分类号： G03F7/26 ,  H01L21/48 ,  H01L23/12 ,  H01L23/52 ,  H05K3/18 ,  H05K3/40 ,  H05K3/10

CPC分类号： H05K3/4007 ,  H01L21/4853 ,  H01L2924/00013 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0577 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

摘要： An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.

摘要翻译： 通过在基板上形成第一层正性光致抗蚀剂，通过在第一层上软化烘烤该第一层并将其暴露在短时间内，用一个整体电路芯片来形成用于安装诸如集成电路芯片的微电子器件的互连柱， 宽孔径面罩或简单的UV空白洪水曝光。 在不显影第一层的情况下，将第二层正性抗蚀剂涂覆在第一层上，软化，然后用窄孔径掩模曝光。 在第二层的软烘烤期间，光致抗蚀剂化合物中的一些活化剂扩散到第一层的暴露部分，并以这样的方式改变其溶解度，使得当这些层随后显影时，显影剂部分地削弱未曝光 第一层的部分以在光致抗蚀剂中形成具有大致均匀横截面的开口。 然后可以通过电镀填充该开口以产生强大的整体互连柱。

公开(公告)号：US5854534A

公开(公告)日：1998-12-29

申请号：US559369

申请日：1995-11-16

申请人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-chou Vincent Wang ,  Larry L. Moresco ,  Teruo Murase

发明人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-chou Vincent Wang ,  Larry L. Moresco ,  Teruo Murase

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H05K1/14 ,  H01L23/52 ,  H01L23/04 ,  H01L23/053 ,  H01L23/34

CPC分类号： H05K1/144 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/66 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011

摘要： An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed though rigid segments and signals are routed though a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected. In another embodiment of the invention, a separate power plate is provided for carrying the power lines. Portions of the power plate, with a multilayered thin film structure thereon, are cut and folded to form interposers. Methods of making single-chip interposers are also disclosed.

摘要翻译： 示出了用于将集成电路芯片安装到基板的插入器基板及其制造方法。 插入器基板包括彼此基本隔离的电源路径和受控阻抗信号路径。 电源通过刚性段传送，信号通过薄膜柔性连接器布线，该连接器从插入器基板的上表面延伸到下表面。 旁路电容被并入到插入器基板中并且连接到电源，使得其非常靠近集成电路芯片。 可以通过在其上形成有通孔的刚性基板上形成包括信号路径的多层薄膜结构来制造插入件，去除离开两端段的基板的中心部分，以及折叠和连接端部段，使得通孔为 连接的。 在本发明的另一实施例中，提供了用于承载电源线的单独的功率板。 在其上具有多层薄膜结构的功率板的部分被切割和折叠以形成插入件。 还公开了制造单芯片插入件的方法。

公开(公告)号：US6102710A

公开(公告)日：2000-08-15

申请号：US70493

申请日：1998-04-30

申请人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-chou Vincent Wang ,  Larry L. Moresco ,  Teruo Murase

发明人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-chou Vincent Wang ,  Larry L. Moresco ,  Teruo Murase

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H05K1/14 ,  H01R12/00

CPC分类号： H05K1/144 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/66 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011

摘要： An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected. In another embodiment of the invention, a separate power plate is provided for carrying the power lines. Portions of the power plate, with a multilayered thin film structure thereon, are cut and folded to form interposers. Methods of making single-chip interposers are also disclosed.

摘要翻译： 示出了用于将集成电路芯片安装到基板的插入器基板及其制造方法。 插入器基板包括彼此基本隔离的电源路径和受控阻抗信号路径。 电源通过刚性段布线，信号通过从内插器基板的上表面延伸到下表面的薄膜柔性连接器。 旁路电容被并入到插入器基板中并且连接到电源，使得其非常靠近集成电路芯片。 可以通过在其上形成有通孔的刚性基板上形成包括信号路径的多层薄膜结构来制造插入件，去除离开两端段的基板的中心部分，以及折叠和连接端部段，使得通孔为 连接的。 在本发明的另一实施例中，提供了用于承载电源线的单独的功率板。 在其上具有多层薄膜结构的功率板的部分被切割和折叠以形成插入件。 还公开了制造单芯片插入件的方法。

公开(公告)号：US5891354A

公开(公告)日：1999-04-06

申请号：US687723

申请日：1996-07-26

申请人： Michael G. Lee ,  Solomon I. Beilin ,  William T. Chou ,  Michael G. Peters ,  Wen-chou Vincent Wang

发明人： Michael G. Lee ,  Solomon I. Beilin ,  William T. Chou ,  Michael G. Peters ,  Wen-chou Vincent Wang

IPC分类号： H01L21/78 ,  H01L23/482 ,  H05K3/00 ,  B44C1/22 ,  H05K3/06

CPC分类号： H01L21/30604 ,  H01L21/78 ,  H01L23/4822 ,  H01L24/01 ,  H01L2924/01029 ,  H05K3/0017

摘要： Methods of wet etching through a silicon substrate using composite etch-stop layers are disclosed. In one embodiment, the composite etch stop comprises a layer of silicon dioxide and a layer of polyimide.

摘要翻译： 公开了通过使用复合蚀刻停止层的硅衬底进行湿蚀刻的方法。 在一个实施例中，复合蚀刻停止件包括二氧化硅层和聚酰亚胺层。

公开(公告)号：US5746903A

公开(公告)日：1998-05-05

申请号：US687716

申请日：1996-07-26

申请人： Solomon I. Beilin ,  William T. Chou ,  Michael G. Lee ,  Wen-chou Vincent Wang

发明人： Solomon I. Beilin ,  William T. Chou ,  Michael G. Lee ,  Wen-chou Vincent Wang

IPC分类号： C25D5/02 ,  C25D5/34 ,  H05K3/42

CPC分类号： C25D5/022 ,  H05K3/422

摘要： Methods of forming high-aspect ratio blind apertures and thereafter filling the apertures with a plating solution are disclosed. A layer of photosensitive material is pattern exposed to actinic radiation to define the apertures, and thereafter exposed to aqueous developer solution. The apertures are then rinsed with water and thereafter exposed to plating solution without drying the aperture of water or developer solution. This is contrary to conventional practice where photoresist layers are dried, and usually post-baked after the development step in order to improve dimensional integrity and reduce swelling of the photoresist material. However, the inventors have recognized that the conventional drying and post-baking steps forever destroy the best opportunity to wet the walls of high-aspect ratio apertures with water, and have discovered that continually maintaining water within the aperture between the development and electroplating steps provides the best opportunity to fill the apertures with plating solution.

摘要翻译： 公开了形成高纵横比盲孔并随后用电镀液填充孔的方法。 感光材料层被图案暴露于光化辐射以限定孔，然后暴露于含水显影剂溶液中。 然后用水冲洗孔，然后暴露于电镀溶液，而不干燥水或显影剂溶液的孔。 这与常规实践相反，其中光致抗蚀剂层被干燥，并且通常在显影步骤后进行后烘烤，以便提高尺寸完整性并减少光致抗蚀剂材料的溶胀。 然而，本发明人已经认识到，传统的干燥和后烘烤步骤永远破坏了用水润湿高纵横比孔的壁的最佳机会，并且已经发现，在显影和电镀步骤之间的孔内持续保持水提供 最好的机会用电镀溶液填充孔。

公开(公告)号：US5942373A

公开(公告)日：1999-08-24

申请号：US13000

申请日：1998-01-26

申请人： William T. Chou ,  Solomon I. Beilin ,  Wen-chou Vincent Wang

发明人： William T. Chou ,  Solomon I. Beilin ,  Wen-chou Vincent Wang

IPC分类号： G03F7/20 ,  G03F7/40

CPC分类号： G03F7/40 ,  G03F7/2026 ,  H01L2924/00013 ,  Y10S430/143

摘要： Methods of forming patterns in photo-sensitive resist layers with high aspect ratio features are described. The photosensitive layer is patterned exposed to actinic radiation and thereafter developed. For high aspect ratio patterns, the inventors have often observed a residue of resist material at the bottom of such features, and that this residue interferes with subsequent processing, such as filling the pattern with metal by a plating operation. To remove this residue, the patterned locations of the resist are exposed to a low dose of low-energy electron beam radiation, preferably having energy of less than 6 KeV and dosage of less than 200 .mu.C/cm.sup.2. After the electron beam exposure, the aperture is again exposed to a developer solution, which may be of the same composition as the developer initially used to develop the patterns.

摘要翻译： 描述了在具有高纵横比特征的光敏抗蚀剂层中形成图案的方法。 感光层被图案化曝光于光化辐射，然后显影。 对于高纵横比图案，本发明人经常在这些特征的底部观察到抗蚀剂材料的残留物，并且该残留物干扰随后的加工，例如通过电镀操作用金属填充图案。 为了除去该残留物，抗蚀剂的图案化位置暴露于低剂量的低能电子束辐射，优选具有小于6KeV的能量和小于200μC/ cm 2的剂量。 在电子束曝光之后，孔再次暴露于显影剂溶液中，显影剂溶液可以与最初用于显影图案的显影剂具有相同的组成。

公开(公告)号：US5789140A

公开(公告)日：1998-08-04

申请号：US639283

申请日：1996-04-25

申请人： William T. Chou ,  Solomon I. Beilin ,  Wen-chou Vincent Wang

发明人： William T. Chou ,  Solomon I. Beilin ,  Wen-chou Vincent Wang

IPC分类号： G03F7/20 ,  G03F7/40

CPC分类号： G03F7/40 ,  G03F7/2026 ,  H01L2924/00013 ,  Y10S430/143

摘要： Methods of forming patterns in photo-sensitive resist layers with high aspect ratio features are described. The photosensitive layer is patterned exposed to actinic radiation and thereafter developed. For high aspect ratio patterns, the inventors have often observed a residue of resist material at the bottom of such features, and that this residue interferes with subsequent processing, such as filling the pattern with metal by a plating operation. To remove this residue, the patterned locations of the resist are exposed to a low dose of low-energy electron beam radiation, preferably having energy of less than 6 KeV and dosage of less than 200 .mu.C/cm.sup.2. After the electron beam exposure, the aperture is again exposed to a developer solution, which may be of the same composition as the developer initially used to develop the patterns.

摘要翻译： 描述了在具有高纵横比特征的光敏抗蚀剂层中形成图案的方法。 感光层被图案化曝光于光化辐射，然后显影。 对于高纵横比图案，本发明人经常在这些特征的底部观察到抗蚀剂材料的残留物，并且该残留物干扰随后的加工，例如通过电镀操作用金属填充图案。 为了除去该残留物，抗蚀剂的图案化位置暴露于低剂量的低能电子束辐射，优选具有小于6KeV的能量和小于200μC/ cm 2的剂量。 在电子束曝光之后，孔再次暴露于显影剂溶液中，显影剂溶液可以与最初用于显影图案的显影剂具有相同的组成。