公开(公告)号：US11262936B2

公开(公告)日：2022-03-01

申请号：US15768597

申请日：2016-07-27

Applicant: SONY CORPORATION

Inventor： Ken Ishii ,  Hiroyuki Iwaki ,  Kenichi Nakanishi ,  Yasushi Fujinami ,  Tatsuo Shinbashi

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/06

Abstract: The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories.
In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.

公开(公告)号：US20210318853A1

公开(公告)日：2021-10-14

申请号：US17258965

申请日：2019-07-12

Applicant: Sony Corporation

Inventor： Takashi Morie ,  Ha karu Tamukoh ,  Quan Wang ,  Yasushi Fujinami

IPC: G06F7/544

Abstract: An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Pulse signals corresponding to input values are input to the plurality of input lines. The multiply-accumulate operation device includes a plurality of multiplication units that generates, on the basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying the input values by weight values, and an output unit that outputs a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values generated by each of the plurality of multiplication units. A value of at least one of the input value or the weight value is limited.

公开(公告)号：US20180143871A1

公开(公告)日：2018-05-24

申请号：US15736079

申请日：2016-04-15

Applicant: Sony Corporation

Inventor： Tatsuo Shinbashi ,  Kenichi Nakanishi ,  Yasushi Fujinami ,  Hiroyuki Iwaki ,  Ken Ishii ,  Hideaki Okubo

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/15 ,  H03M13/09

CPC classification number: G06F11/10 ,  G06F11/1012 ,  G06F12/16 ,  G11C16/02 ,  G11C16/06 ,  H03M13/09 ,  H03M13/095 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/35 ,  H03M13/611

Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell.A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.

公开(公告)号：US09608668B2

公开(公告)日：2017-03-28

申请号：US14528555

申请日：2014-10-30

Applicant: Sony Corporation

Inventor： Ryoji Ikegaya ,  Tatsuo Shinbashi ,  Yasushi Fujinami

IPC: H03M13/00 ,  H03M13/15

CPC classification number: H03M13/152 ,  H03M13/1535 ,  H03M13/1545 ,  H03M13/1585 ,  H03M13/6502

Abstract: Provided is an error correcting method including: executing, by an error-position detector, a determination process if a received word fails to satisfy a predetermined condition, the received word having a plurality of symbols, the determination process including determining if a determination-target symbol has an error or not, and detecting an error position, the error position being a position of the symbol having an error; changing, by a determination-target changing unit, the position of the determination-target symbol of the received word every time the determination process is executed; detecting, by an undetected-position detector, if the predetermined condition is satisfied, the error position of the symbol, for which the determination process is not executed, based on a relation between the error position and a variable generated from the received word; and correcting, by an error corrector, an error at the error position detected by the error-position detector and the undetected-position detector.

公开(公告)号：US09542270B2

公开(公告)日：2017-01-10

申请号：US14318927

申请日：2014-06-30

Applicant: Sony Corporation

Inventor： Lui Sakai ,  Keiichi Tsutsui ,  Yasushi Fujinami

IPC: G11C29/00 ,  G06F11/10 ,  G11B20/18

CPC classification number: G06F11/1076 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1064 ,  G11B20/1833

Abstract: An error detection-correction unit reads system information for operating a system from a first memory and performs error detection-correction processing. A control unit supplies the system information to a host computer in a case where the error detection-correction processing is successful. In addition, the control unit reads a backup of the system information from a second memory that is different from the first memory and supplies the backup of the system information to the host computer in a case where the detection-correction processing fails.

Abstract translation: 错误检测校正单元从第一存储器读取用于操作系统的系统信息，并执行错误检测校正处理。 在错误检测校正处理成功的情况下，控制单元将系统信息提供给主计算机。 此外，控制单元从与第一存储器不同的第二存储器读取系统信息的备份，并且在检测校正处理失败的情况下将系统信息的备份提供给主计算机。

公开(公告)号：US09361952B2

公开(公告)日：2016-06-07

申请号：US13780655

申请日：2013-02-28

Applicant: Sony Corporation

Inventor： Kenichi Nakanishi ,  Keiichi Tsutsui ,  Yasushi Fujinami ,  Naohiro Adachi ,  Hideaki Okubo ,  Ken Ishii ,  Tatsuo Shinbashi

IPC: G11C7/00 ,  G11C7/10

CPC classification number: G11C7/00 ,  G11C7/1006

Abstract: Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data.

Abstract translation: 这里公开了一种存储控制装置，包括：判定部，被配置为判定在二进制值之间的特定值的位数是否大于至少部分输入数据的参考值，该存储单元执行重写 到二进制值中的一个并且在写入过程中按顺序重写到另一个二进制值，以产生指示决定结果的决定数据; 以及写入侧输出部分，被配置为当确定所述位数大于所述参考值时，输出至少部分所述输入数据与所述决定数据一起作为写入数据被反转为所述存储器单元。

公开(公告)号：US09280455B2

公开(公告)日：2016-03-08

申请号：US13945987

申请日：2013-07-19

Applicant: Sony Corporation

Inventor： Naohiro Adachi ,  Keiichi Tsutsui ,  Ken Ishii ,  Hideaki Okubo ,  Kenichi Nakanishi ,  Yasushi Fujinami ,  Tatsuo Shinbashi ,  Lui Sakai ,  Ryoji Ikegaya

IPC: G06F12/02 ,  G06F12/00 ,  G11C13/00

CPC classification number: G06F12/00 ,  G11C13/0002 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2213/78

Abstract: Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.

Abstract translation: 提供了一种存储器控制装置，包括顺序地指定存储块的写入控制单元，将写入数据写入指定的存储器块的写入处理单元，从存储器块读取读取的数据并验证是否 读取数据与多个存储器单元中的每一个的写入数据相匹配，重试禁止单元禁止在读取数据与多个存储器单元中的写入数据匹配的存储器单元中进行重试处理，并且重试 控制单元，其指定所述多个存储器块中的至少一些存储块，并且当读取数据与写入所有写入数据的所述多个存储器单元中的任何一个存储器单元中的写入数据不匹配时，同时执行重试处理。

公开(公告)号：US20140059404A1

公开(公告)日：2014-02-27

申请号：US13953960

申请日：2013-07-30

Applicant: Sony Corporation

Inventor： Hideaki Okubo ,  Keiichi Tsutsui ,  Yasushi Fujinami ,  Kenichi Nakanishi ,  Naohiro Adachi ,  Ken Ishii ,  Tatsuo Shinbashi

IPC: G06F11/10 ,  G06F12/08

CPC classification number: G06F11/1016 ,  G06F11/1068 ,  G06F12/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2029/0411

Abstract: There is provided a memory control device, including a request determining unit that determines a type of a request, and a control unit that writes read data read from a memory cell array in the memory cell array in units of predetermined pages of the memory cell array when the request is a refresh request, and divides the page of write data into units of groups and writes the page of the write data in the memory cell array over twice or more when the request is a write request.

Abstract translation: 提供了一种存储器控制装置，包括确定请求的类型的请求确定单元，以及以存储单元阵列的预定页为单位将从存储单元阵列读出的读取数据写入存储单元阵列的控制单元 当请求是刷新请求时，并且当请求是写入请求时，将写入数据的页面划分成组的单元并将写入数据的页面写入存储单元阵列中两次或更多次。

公开(公告)号：US20130272078A1

公开(公告)日：2013-10-17

申请号：US13780655

申请日：2013-02-28

Applicant: SONY CORPORATION

Inventor： Kenichi Nakanishi ,  Keiichi Tsutsui ,  Yasushi Fujinami ,  Naohiro Adachi ,  Hideaki Okubo ,  Ken Ishii ,  Tatsuo Shinbashi

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/1006

Abstract: Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data.

Abstract translation: 这里公开了一种存储控制装置，包括：判定部，被配置为判定在二进制值之间的特定值的位数是否大于至少部分输入数据的参考值，该存储单元执行重写 到二进制值中的一个并且在写入过程中按顺序重写到另一个二进制值，以产生指示决定结果的决定数据; 以及写入侧输出部分，被配置为当确定所述位数大于所述参考值时，输出至少部分所述输入数据与所述决定数据一起作为写入数据被反转为所述存储器单元。

公开(公告)号：US11900184B2

公开(公告)日：2024-02-13

申请号：US16973237

申请日：2019-07-05

Applicant: Sony Corporation

Inventor： Yasushi Fujinami ,  Hiroyuki Yamagishi

IPC: G06F7/544 ,  G06G7/60 ,  G06G7/16 ,  G06G7/184 ,  G06N3/049

CPC classification number: G06G7/60 ,  G06F7/5443 ,  G06G7/16 ,  G06G7/184 ,  G06N3/049

Abstract: A multiply-accumulate device (10) includes: a comparison unit (18) that compares, with a threshold voltage, a voltage generated by an electric charge stored in a storage unit (14), and outputs an output signal at timing at which the voltage exceeds the threshold voltage; and a control circuit (110) that reduces, based on a predetermined set value, a charging current to the storage unit (14) from a plurality of input units (13) connected to the storage unit (14).