公开(公告)号：US10481971B2

公开(公告)日：2019-11-19

申请号：US15736079

申请日：2016-04-15

Applicant: Sony Corporation

Inventor： Tatsuo Shinbashi ,  Kenichi Nakanishi ,  Yasushi Fujinami ,  Hiroyuki Iwaki ,  Ken Ishii ,  Hideaki Okubo

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/09 ,  H03M13/35 ,  H03M13/00 ,  G11C16/02 ,  G11C16/06 ,  H03M13/15 ,  H03M13/19

Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell.A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.

公开(公告)号：US20170293513A1

公开(公告)日：2017-10-12

申请号：US15507413

申请日：2015-07-22

Applicant: Sony Corporation

Inventor： Tatsuo Shinbashi ,  Keiichi Tsutsui ,  Hideaki Okubo ,  Lui Sakai ,  Kenichi Nakanishi ,  Yasushi Fujinami

IPC: G06F11/00 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/004 ,  G06F3/0619 ,  G06F12/16 ,  G11C7/1006 ,  G11C13/00 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C29/52

Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells.[Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.

公开(公告)号：US20140129904A1

公开(公告)日：2014-05-08

申请号：US14049248

申请日：2013-10-09

Applicant: SONY CORPORATION

Inventor： Lui Sakai ,  Yasushi Fujinami ,  Naohiro Adachi ,  Keiichi Tsutsui ,  Tatsuo Shinbashi ,  Ryoji Ikegaya

IPC: G06F11/10

CPC classification number: G06F11/1012 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/373 ,  H03M13/6306

Abstract: An error detection and correction apparatus includes a code word read-out unit to execute read processing to read out a code word including a plurality of code elements by detection of an erasure position as read data from a memory address and to execute re-read processing to read out the code word as re-read data from the memory address after a predetermined time is elapsed from the time to read out the read data; a timing control erasure position detection unit to detect a position of the code element having a value not matched as the erasure position in the code word by determining whether or not the value is matched per the code word in the read data and the re-read data; and an error correction unit to correct an error based on the erasure position in the code word where the erasure position is detected.

Abstract translation: 错误检测和校正装置包括：码字读出单元，用于执行读取处理，以通过从存储器地址检测作为读取数据的擦除位置读出包括多个代码元素的代码字，并执行重新读取处理 在从读出数据的时间经过预定时间之后，将代码字读出为来自存储器地址的重新读取数据; 定时控制擦除位置检测单元，通过根据读取的数据中的代码字是否匹配值和重新读取来检测具有与码字中的擦除位置不匹配的值的代码元素的位置 数据; 以及错误校正单元，用于基于检测到擦除位置的代码字中的擦除位置校正错误。

公开(公告)号：US20130262737A1

公开(公告)日：2013-10-03

申请号：US13781260

申请日：2013-02-28

Applicant: SONY CORPORATION

Inventor： Kenichi Nakanishi ,  Keiichi Tsutsui ,  Yasushi Fujinami ,  Naohiro Adachi ,  Ken Ishii ,  Hideaki Okubo ,  Tatsuo Shinbashi

IPC: G06F12/06

CPC classification number: G06F12/0623 ,  G06F12/06 ,  G06F12/0607

Abstract: Disclosed herein is a storage control apparatus including: a command processing section configured to receive a command requesting accesses to a plurality of access units by specifying an address in a memory space including a plurality of banks; and an address generating section configured to generate an address of an access unit serving as an object of the accesses in a bank selected from the banks as a bank determined in advance for the specified address.

Abstract translation: 这里公开了一种存储控制装置，包括：命令处理部，被配置为通过在包括多个存储体的存储空间中指定地址来接收请求对多个访问单元的访问的命令; 以及地址生成部，被配置为生成作为从所述存储体中选择的存储体中的访问对象的访问单元的地址作为对于所述指定地址预先确定的存储体。

公开(公告)号：US11029881B2

公开(公告)日：2021-06-08

申请号：US16311100

申请日：2017-04-17

Applicant: SONY CORPORATION

Inventor： Ken Ishii ,  Hiroyuki Iwaki ,  Kenichi Nakanishi ,  Yasushi Fujinami ,  Tatsuo Shinbashi

IPC: G06F3/06 ,  G06F11/10

Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.

公开(公告)号：US10545804B2

公开(公告)日：2020-01-28

申请号：US15507413

申请日：2015-07-22

Applicant: Sony Corporation

Inventor： Tatsuo Shinbashi ,  Keiichi Tsutsui ,  Hideaki Okubo ,  Lui Sakai ,  Kenichi Nakanishi ,  Yasushi Fujinami

IPC: G06F11/00 ,  G06F3/06 ,  G11C29/52

Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells.[Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.

公开(公告)号：US09417956B2

公开(公告)日：2016-08-16

申请号：US14154918

申请日：2014-01-14

Applicant: Sony Corporation

Inventor： Lui Sakai ,  Ryoji Ikegaya ,  Tatsuo Shinbashi ,  Kenichi Nakanishi ,  Yasushi Fujinami ,  Makiko Yamamoto

IPC: H03M13/00 ,  G06F11/10

CPC classification number: G06F11/1012

Abstract: An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in chains and being a code word containing a plurality of partial data; and a second-code error correction section configured to correct the error in one partial data containing the first code word in which the error is detected of the plurality of partial data in the second code word, based on adjacent partial data adjacent to the one partial data.

Abstract translation: 错误检测和校正单元包括：第一代码错误检测部分，被配置为检测第二代码字中的多个第一代码字中的每一个是否具有错误，通过对多个第一代码进行编码而生成的第二代码字 链中的单词和包含多个部分数据的代码字; 以及第二码错误校正部，被配置为基于与所述一个部分相邻的相邻部分数据来校正包含检测到所述第二码字中的所述多个部分数据的所述错误的第一码字的一个部分数据中的所述错误 数据。

公开(公告)号：US09229714B2

公开(公告)日：2016-01-05

申请号：US13873679

申请日：2013-04-30

Applicant: Sony Corporation

Inventor： Ken Ishii ,  Keiichi Tsutsui ,  Yasushi Fujinami ,  Kenichi Nakanishi ,  Naohiro Adachi ,  Hideaki Okubo ,  Tatsuo Shinbashi

IPC: G06F9/30 ,  G11C7/10 ,  G11C16/06

CPC classification number: G06F9/3004 ,  G11C7/1006 ,  G11C16/06

Abstract: There is provided a memory control apparatus including: a pre-read processing section reading pre-read data from a data area to be written to before a write process in a predetermined data area of a memory cell array; a conversion determination section which, upon selectively allowing the pre-read data to transition to either a first conversion candidate or a second conversion candidate of the write data to be written in the write process, generates a determination result for selecting either of the candidates based on the larger of two values of which one is the number of bits transitioning from the first value to the second value and of which the other is the number of bits transitioning from the second value to the first value; and a conversion control section selecting either of the candidates in accordance with the determination result.

Abstract translation: 提供了一种存储器控制装置，包括：预读取处理部分，从存储单元阵列的预定数据区域中的写入处理之前的待写入数据区域读取预读数据; 转换确定部分，在选择性地允许预读数据转换到要在写入处理中写入的写数据的第一转换候选或第二转换候选时，产生用于选择候选的任一个的确定结果 在两个值中的较大者中，一个是从第一值转换到第二值的位数，另一个是从第二值转换到第一值的位数; 以及转换控制部分，根据确定结果选择候选者之一。

公开(公告)号：US09202563B2

公开(公告)日：2015-12-01

申请号：US13855155

申请日：2013-04-02

Applicant: Sony Corporation

Inventor： Yasushi Fujinami ,  Naohiro Adachi ,  Ken Ishii ,  Hideaki Okubo ,  Keiichi Tsutsui ,  Kenichi Nakanishi ,  Tatsuo Shinbashi

IPC: G11C13/00 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1072 ,  G11C7/22 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/79

Abstract: A storage controlling apparatus includes a command decoder and command processing section. The command decoder decides whether or not a plurality of access object addresses of different commands included in a command string correspond to words different from each other in a same one of blocks of a memory cell array which have a common plate. The command processing section collectively and successively executes, when it is decided that the access object addresses of the commands correspond to the words different from each other in the same block of the memory cell array, those of operations in processing of the commands in which an equal voltage is applied as a drive voltage between the plate and a bit line.

Abstract translation: 存储控制装置包括命令解码器和命令处理部分。 命令解码器判定包括在命令串中的不同命令的多个访问对象地址是否与具有共同的板的存储单元阵列的相同块中的彼此不同的字对应。 命令处理部分在确定命令的访问对象地址对应于存储单元阵列的同一块中彼此不同的字时，共同并依次执行处理其中的命令的操作 作为板和位线之间的驱动电压施加相等的电压。

公开(公告)号：US09170893B2

公开(公告)日：2015-10-27

申请号：US13827926

申请日：2013-03-14

Applicant: Sony Corporation

Inventor： Hideaki Okubo ,  Keiichi Tsutsui ,  Kenichi Nakanishi ,  Yasushi Fujinami ,  Naohiro Adachi ,  Ken Ishii ,  Tatsuo Shinbashi

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/10

CPC classification number: G06F11/167 ,  G06F11/1048

Abstract: Disclosed herein is a storage controlling apparatus, including: a status acquisition section configured to acquire status including a number of times of execution of verification after writing into a memory from the memory; a history information retention section configured to retain a history of the status as history information in an associated relationship with each of predetermined regions of the memory; and a region selection section configured to select a region which satisfies a condition in accordance with the history information when a new region is to be used in the memory.

Abstract translation: 这里公开了一种存储控制装置，包括：状态获取部，被配置为从存储器写入到存储器中，获取包括执行验证次数的状态; 历史信息保持部，被配置为将所述状态的历史保持为与所述存储器的每个预定区域相关联的历史信息; 以及区域选择部，被配置为当在存储器中使用新的区域时，选择满足与历史信息相关的条件的区域。