公开(公告)号：US06849536B2

公开(公告)日：2005-02-01

申请号：US10404210

申请日：2003-04-01

申请人： Soo-Geun Lee ,  Ju-Hyuk Chung ,  Il-Goo Kim ,  Kyoung-Woo Lee ,  Wan-Jae Park ,  Jae-Hak Kim

发明人： Soo-Geun Lee ,  Ju-Hyuk Chung ,  Il-Goo Kim ,  Kyoung-Woo Lee ,  Wan-Jae Park ,  Jae-Hak Kim

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4762

CPC分类号： H01L21/76831 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76835 ,  H01L2221/1036

摘要： Provided are an inter-metal dielectric pattern and a method of forming the same. The pattern includes a lower interconnection disposed on a semiconductor substrate, a lower dielectric layer having a via hole exposing the lower interconnection and covering the semiconductor substrate where the lower interconnection is disposed, and an upper dielectric pattern and a lower capping pattern, which include a trench line exposing the via hole and sequentially stacked on the lower dielectric layer. The lower dielectric layer and the upper dielectric pattern are low k-dielectric layers formed of materials such as SiO2, SiOF, SiOC, and porous dielectric. The method includes forming an inter-metal dielectric layer including a lower dielectric layer and upper dielectric layer, which are sequentially stacked, on a lower interconnection formed on a semiconductor substrate. The inter-metal dielectric layer is patterned to form a via hole, which exposes the upper side of the lower interconnection. Then, an upper capping layer is formed on the entire surface of the semiconductor substrate including the via hole. The upper capping layer and the upper dielectric layer are successively patterned to form a trench line exposing the upper side of the via hole. The upper capping layer is formed of at least one material selected from the group consisting of a silicon oxide layer, a silicon carbide layer, a silicon nitride layer, and a silicon oxynitride layer, by using PECVD.

摘要翻译： 提供了金属间介电图案及其形成方法。 该图案包括布置在半导体衬底上的下部互连，具有通孔暴露下部互连并覆盖半导体衬底的下部电介质图案和下部封盖图案的下部电介质层， 沟槽线暴露通孔并依次堆叠在下介电层上。 下电介质层和上电介质图案是由诸如SiO 2，SiOF，SiOC和多孔电介质的材料形成的低K电介质层。 该方法包括在形成在半导体衬底上的下互连件上依次层叠包括下电介质层和上电介质层的金属间电介质层。 图案化金属间电介质层以形成通孔，其暴露下部互连的上侧。 然后，在包括通孔的半导体衬底的整个表面上形成上覆盖层。 上覆盖层和上电介质层被连续地图案化以形成暴露通孔上侧的沟槽线。 通过使用PECVD，上覆盖层由选自氧化硅层，碳化硅层，氮化硅层和氮氧化硅层的至少一种材料形成。

公开(公告)号：US07560332B2

公开(公告)日：2009-07-14

申请号：US11733711

申请日：2007-04-10

申请人： Kyoung-Woo Lee ,  Wan-Jae Park ,  Jeong-Hoon Ahn ,  Kyung-Tae Lee ,  Mu-Kyeng Jung ,  Yong-Jun Lee ,  Il-Goo Kim ,  Soo-Geun Lee

发明人： Kyoung-Woo Lee ,  Wan-Jae Park ,  Jeong-Hoon Ahn ,  Kyung-Tae Lee ,  Mu-Kyeng Jung ,  Yong-Jun Lee ,  Il-Goo Kim ,  Soo-Geun Lee

IPC分类号： H01L21/8234

CPC分类号： H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

摘要翻译： 本发明的实施例包括具有高电容的MIM电容器，其可以在没有影响现有技术的问题的情况下被制造。 这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。 可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。 将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

公开(公告)号：US07033944B2

公开(公告)日：2006-04-25

申请号：US10654770

申请日：2003-09-04

申请人： Wan-Jae Park ,  Il-Goo Kim ,  Sang-Rok Hah ,  Kyoung-Woo Lee

发明人： Wan-Jae Park ,  Il-Goo Kim ,  Sang-Rok Hah ,  Kyoung-Woo Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/76808

摘要： A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.

摘要翻译： 公开了一种双镶嵌工艺。 根据本发明的双镶嵌工艺，通过金属间电介质层的第一凹陷区域填充有底部保护层，同时蚀刻底部保护层和金属间电介质层，以形成第二凹陷区域，该凹陷区域具有 通过使用蚀刻气体相对于底部保护层选择性地蚀刻金属间电介质层，比第一凹陷区域上的第一凹陷区域更浅的深度和更宽的宽度。 换句话说，相对于底部保护层的蚀刻选择比，金属间电介质层优选为约0.5至约1.5。 因此，可以形成双重镶嵌结构而不形成副产物或氧化物栅栏。

公开(公告)号：US07157366B2

公开(公告)日：2007-01-02

申请号：US10888577

申请日：2004-07-09

申请人： Il-Goo Kim ,  Sang-Rok Hah ,  Sae-il Son ,  Kyoung-Woo Lee

发明人： Il-Goo Kim ,  Sang-Rok Hah ,  Sae-il Son ,  Kyoung-Woo Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76813

摘要： Various methods are provided for forming metal interconnection layers of semiconductor devices. One exemplary method for forming a metal interconnection layer of a semiconductor device includes forming an interlayer dielectric layer on a substrate, forming a hard mask layer on the interlayer dielectric layer, wherein the hard mask layer serves as an anti-reflection layer, depositing and patterning a first photoresist layer to form a first photoresist pattern on the hard mask layer, forming a partial via hole in the interlayer dielectric layer by etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask, removing the first photoresist pattern, depositing a second photoresist layer to fill the partial via hole with photoresist material and patterning the second photoresist layer to form a second photoresist pattern that defines a trench interconnection area which overlaps at least portion of the partial via hole, etching the hard mask layer using the second photoresist pattern as an etching mask to form a hard mask pattern, completely removing the second photoresist pattern and the photoresist material in the partial via hole, etching the interlayer dielectric layer using the hard mask pattern as an etching mask to form the trench interconnection area and to extend the partial via hole to form a full via hole, and filling the full via hole and the trench interconnection area with a conductive material.

摘要翻译： 提供用于形成半导体器件的金属互连层的各种方法。 用于形成半导体器件的金属互连层的一种示例性方法包括在衬底上形成层间电介质层，在层间介质层上形成硬掩模层，其中硬掩模层用作抗反射层，沉积和图案化 第一光致抗蚀剂层，以在硬掩模层上形成第一光致抗蚀剂图案，通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，在层间电介质层中形成部分通孔， 沉积第二光致抗蚀剂层以用光致抗蚀剂材料填充部分通孔并且图案化第二光致抗蚀剂层以形成第二光致抗蚀剂图案，其限定与部分通孔的至少部分重叠的沟槽互连区域，蚀刻硬掩模 层，使用第二光致抗蚀剂图案作为蚀刻掩模以形成硬掩模图案 n，完全去除部分通孔中的第二光致抗蚀剂图案和光致抗蚀剂材料，使用硬掩模图案作为蚀刻掩模蚀刻层间介电层，以形成沟槽互连区域并延伸部分通孔以形成完整通孔 并且用导电材料填充整个通孔和沟槽互连区域。

公开(公告)号：US20050037605A1

公开(公告)日：2005-02-17

申请号：US10888577

申请日：2004-07-09

申请人： Il-Goo Kim ,  Sang-Rok Hah ,  Sae-il Son ,  Kyoung-Woo Lee

发明人： Il-Goo Kim ,  Sang-Rok Hah ,  Sae-il Son ,  Kyoung-Woo Lee

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76813

摘要： Various methods are provided for forming metal interconnection layers of semiconductor devices. One exemplary method for forming a metal interconnection layer of a semiconductor device includes forming an interlayer dielectric layer on a substrate, forming a hard mask layer on the interlayer dielectric layer, wherein the hard mask layer serves as an anti-reflection layer, depositing and patterning a first photoresist layer to form a first photoresist pattern on the hard mask layer, forming a partial via hole in the interlayer dielectric layer by etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask, removing the first photoresist pattern, depositing a second photoresist layer to fill the partial via hole with photoresist material and patterning the second photoresist layer to form a second photoresist pattern that defines a trench interconnection area which overlaps at least portion of the partial via hole, etching the hard mask layer using the second photoresist pattern as an etching mask to form a hard mask pattern, completely removing the second photoresist pattern and the photoresist material in the partial via hole, etching the interlayer dielectric layer using the hard mask pattern as an etching mask to form the trench interconnection area and to extend the partial via hole to form a full via hole, and filling the full via hole and the trench interconnection area with a conductive material.

摘要翻译： 提供用于形成半导体器件的金属互连层的各种方法。 用于形成半导体器件的金属互连层的一种示例性方法包括在衬底上形成层间电介质层，在层间介质层上形成硬掩模层，其中硬掩模层用作抗反射层，沉积和图案化 第一光致抗蚀剂层，以在硬掩模层上形成第一光致抗蚀剂图案，通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，在层间电介质层中形成部分通孔， 沉积第二光致抗蚀剂层以用光致抗蚀剂材料填充部分通孔并且图案化第二光致抗蚀剂层以形成第二光致抗蚀剂图案，其限定与部分通孔的至少部分重叠的沟槽互连区域，蚀刻硬掩模 层，使用第二光致抗蚀剂图案作为蚀刻掩模以形成硬掩模图案 n，完全去除部分通孔中的第二光致抗蚀剂图案和光致抗蚀剂材料，使用硬掩模图案作为蚀刻掩模蚀刻层间介电层，以形成沟槽互连区域并延伸部分通孔以形成完整通孔 并且用导电材料填充整个通孔和沟槽互连区域。

公开(公告)号：US20080124917A1

公开(公告)日：2008-05-29

申请号：US11986236

申请日：2007-11-20

申请人： Jun-Hwan Oh ,  Ju-Hyuck Chung ,  Il-Goo Kim ,  Hyoung-Sik Kim

发明人： Jun-Hwan Oh ,  Ju-Hyuck Chung ,  Il-Goo Kim ,  Hyoung-Sik Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76885

摘要： In a method of manufacturing a semiconductor device having air gaps, an organic sacrificial layer pattern is formed on a semiconductor substrate, wherein the organic sacrificial layer pattern includes openings. Metal structures are formed in the openings. The organic sacrificial layer pattern is removed by a plasma ashing treatment using a source gas including oxygen (O2) and carbon monoxide (CO). An insulating interlayer is formed to have air gaps between the metal structures. Resistance-capacitance (RC) delay and crosstalk between the metal structures may be efficiently suppressed.

摘要翻译： 在制造具有气隙的半导体器件的方法中，在半导体衬底上形成有机牺牲层图案，其中有机牺牲层图案包括开口。 金属结构形成在开口中。 通过使用包括氧（O 2/2）和一氧化碳（CO））的源气体的等离子体灰化处理来去除有机牺牲层图案。 形成绝缘中间层以在金属结构之间具有气隙。 可以有效地抑制金属结构之间的电阻 - 电容（RC）延迟和串扰。

公开(公告)号：US20080073787A1

公开(公告)日：2008-03-27

申请号：US11655156

申请日：2007-01-19

申请人： Jun-Hwan Oh ,  Hyoung-Sik Kim ,  Il-Goo Kim ,  Ju-Hyuck Chung

发明人： Jun-Hwan Oh ,  Hyoung-Sik Kim ,  Il-Goo Kim ,  Ju-Hyuck Chung

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/2885 ,  H01L21/32134 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76877

摘要： A metal (e.g., copper) interconnect and related method of fabrication are disclosed in which the metal interconnect is formed by electro-plating a seed layer formed on a recess in a substrate before a metal layer is electro-plated to fill the recess.

摘要翻译： 公开了一种金属（例如铜）互连和相关的制造方法，其中通过在金属层被电镀以填充凹部之前，通过电镀电镀在形成于基板的凹部上的种子层来形成金属互连。

公开(公告)号：US06924228B2

公开(公告)日：2005-08-02

申请号：US10748900

申请日：2003-12-30

申请人： Il-Goo Kim ,  Sang-Rok Hah

发明人： Il-Goo Kim ,  Sang-Rok Hah

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76829

摘要： A method of forming a via contact structure using a dual damascene technique is provided. The method includes forming a lower interconnection line on a semiconductor substrate and sequentially forming an inter-metal dielectric layer and a hard mask layer on the semiconductor substrate having the lower interconnection line. The hard mask layer and the inter-metal dielectric layer are successivley patterned to form a via hole that exposes the lower interconnnection line. A sacrificial layer filling the via hole is formed on the hard mask layer. The sacrificial layer and the hard mask layer are patterned to form a first sacrificial layer pattern having an opening that crosses over the via hole and a second sacrificial layer pattern that remains in the via hole and to simultaneously form a hard mask pattern underneath the first sacrificial layer pattern. The inter-metal dielectric layer is partially etched using the hard mask pattern as an etching mask, thereby forming a trench in the inter-metal dielectric layer. The second sacrificial layer pattern is selectively removed to expose the the lower interconnection line.

摘要翻译： 提供了一种使用双镶嵌技术形成通孔接触结构的方法。 该方法包括在半导体衬底上形成下互连线，并且在具有下互连线的半导体衬底上依次形成金属间介电层和硬掩模层。 硬掩模层和金属间介电层被成功地图案化以形成暴露下部连接线的通孔。 在硬掩模层上形成填充通孔的牺牲层。 牺牲层和硬掩模层被图案化以形成具有穿过通孔的开口的第一牺牲层图案和保留在通孔中的第二牺牲层图案，并且同时在第一牺牲层下方形成硬掩模图案 层图案。 使用硬掩模图案作为蚀刻掩模来部分地蚀刻金属间介电层，从而在金属间介电层中形成沟槽。 选择性地去除第二牺牲层图案以暴露下部互连线。

公开(公告)号：US06699749B1

公开(公告)日：2004-03-02

申请号：US10429321

申请日：2003-05-05

申请人： Seung-Gun Lee ,  Il-Goo Kim ,  Ho-Sen Chang ,  Ju-Hyuk Chang ,  Sang-Rok Hah

发明人： Seung-Gun Lee ,  Il-Goo Kim ,  Ho-Sen Chang ,  Ju-Hyuk Chang ,  Sang-Rok Hah

IPC分类号： H01L218242

CPC分类号： H01L21/02071 ,  H01L21/32136 ,  H01L28/60

摘要： A method of manufacturing a MIM capacitor having a bottom electrode is provided by forming a metal wire including copper on a substrate. After the metal wire is formed on the substrate, a dielectric film is formed on the metal wire. A top electrode film is formed on the dielectric film, and then the top electrode film is etched to form a top electrode. A hard metallic polymer formed during the etching of the top electrode film is removed using a mixture of an oxygen gas and a fluorocarbon based gas. The lifting of the thin films is effectively prevented, and the yield of the manufacturing process for manufacturing a MIM capacitor is increased. Additionally, the MIM capacitor has a uniform capacitance because the damage to the dielectric film is prevented, and the oxidation of the bottom electrode is also prevented.

摘要翻译： 通过在基板上形成包含铜的金属线来提供制造具有底部电极的MIM电容器的方法。 在基板上形成金属线之后，在金属线上形成电介质膜。 在电介质膜上形成顶部电极膜，然后蚀刻顶部电极膜以形成顶部电极。 使用氧气和碳氟化合物气体的混合物除去在顶部电极膜的蚀刻期间形成的硬质金属聚合物。 有效地防止薄膜的提升，并且制造MIM电容器的制造工艺的成品率提高。 此外，MIM电容器具有均匀的电容，因为防止对电介质膜的损坏，并且还防止了底部电极的氧化。

公开(公告)号：US06617232B2

公开(公告)日：2003-09-09

申请号：US10190478

申请日：2002-07-09

申请人： Il-Goo Kim ,  Jae-Seung Hwang

发明人： Il-Goo Kim ,  Jae-Seung Hwang

IPC分类号： H01L2144

CPC分类号： H01L21/76808

摘要： A method of forming electric wiring using a dual damascene process wherein prevention of damage to a lower conductive pattern and low contact resistance may be achieved. A first insulation layer having a first trench filled with a conductive material is formed on a semiconductor substrate. A first etch stop layer, a second insulation layer and a third insulation layer are sequentially formed thereon. A capping layer is formed on the third insulation layer. A via hole is formed by selectively etching the capping layer, third insulation layer and second insulation layer. Then the capping layer is partially etched and a polymer layer is formed on the exposed first etch stop layer. A second trench is formed and the electric wiring is formed by filling a conductive material in a resulting structure. The polymer layer prevents damage to the conductive pattern by protecting the first etch stop layer.

摘要翻译： 使用双镶嵌工艺形成电布线的方法，其中可以实现防止对较低导电图案的损坏和低接触电阻。 在半导体衬底上形成具有填充有导电材料的第一沟槽的第一绝缘层。 在其上依次形成第一蚀刻停止层，第二绝缘层和第三绝缘层。 在第三绝缘层上形成覆盖层。 通过选择性地蚀刻覆盖层，第三绝缘层和第二绝缘层来形成通孔。 然后，覆盖层被部分蚀刻，并且在暴露的第一蚀刻停止层上形成聚合物层。 形成第二沟槽，并且通过在所得到的结构中填充导电材料形成电布线。 聚合物层通过保护第一蚀刻停止层来防止导电图案的损坏。