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    Stacked capacitor and method for producing stacked capacitors for dynamic memory cells
    1.
    发明申请
    Stacked capacitor and method for producing stacked capacitors for dynamic memory cells 失效
    叠层电容器和用于制造用于动态存储单元的叠层电容器的方法

    公开(公告)号：US20070059893A1

    公开(公告)日：2007-03-15

    申请号：US11518504

    申请日：2006-09-07

    申请人： Stephan Kudelka ,  Peter Moll ,  Stefan Jakschik ,  Odo Wunnicke

    发明人： Stephan Kudelka ,  Peter Moll ,  Stefan Jakschik ,  Odo Wunnicke

    IPC分类号： H01L21/336

    CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852

    摘要： A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

    摘要翻译： 一种方法产生用于动态存储单元的堆叠电容器，其中在掩模层（40）中形成有多个沟槽（48），每个沟槽（48）布置在相应的接触插塞（26）的上方并从顶部 屏蔽层（40）的至少部分（42）连接到接触插塞（26）。 为了形成叠层电容器（12）的第一电极（60），导电层（50）覆盖沟槽（48）的侧壁（49）和接触插塞（26）。 在远离接触堆叠（26）的上部区域（63）中，导电层（50）由绝缘层代替，使得在任何粘附的情况下不可能出现短路 在相邻电极之间。

    Stacked capacitor and method for producing stacked capacitors for dynamic memory cells
    2.
    发明授权
    Stacked capacitor and method for producing stacked capacitors for dynamic memory cells 失效
    叠层电容器和用于制造用于动态存储单元的叠层电容器的方法

    公开(公告)号：US07413951B2

    公开(公告)日：2008-08-19

    申请号：US11518504

    申请日：2006-09-07

    申请人： Stephan Kudelka ,  Peter Moll ,  Stefan Jakschik ,  Odo Wunnicke

    发明人： Stephan Kudelka ,  Peter Moll ,  Stefan Jakschik ,  Odo Wunnicke

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852

    摘要： A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

    摘要翻译： 一种方法产生用于动态存储单元的堆叠电容器，其中在掩模层（40）中形成有多个沟槽（48），每个沟槽（48）布置在相应的接触插塞（26）的上方并从顶部 屏蔽层（40）的至少部分（42）连接到接触插塞（26）。 为了形成叠层电容器（12）的第一电极（60），导电层（50）覆盖沟槽（48）的侧壁（49）和接触插塞（26）。 在远离接触堆叠（26）的上部区域（63）中，导电层（50）由绝缘层代替，使得在任何粘附的情况下不可能出现短路 在相邻电极之间。

    Method for patterning ceramic layers
    4.
    发明授权
    Method for patterning ceramic layers 失效
    图案化陶瓷层的方法

    公开(公告)号：US06953722B2

    公开(公告)日：2005-10-11

    申请号：US10425461

    申请日：2003-04-29

    申请人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht ,  Stefan Jakschik ,  Stephan Kudelka ,  Uwe Schröder ,  Matthias Schmeide

    发明人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht ,  Stefan Jakschik ,  Stephan Kudelka ,  Uwe Schröder ,  Matthias Schmeide

    IPC分类号： H01L21/311 ,  H01L21/8242

    CPC分类号： H01L27/10867 ,  H01L21/31133

    摘要： In a method for forming patterned ceramic layers, a ceramic material is deposited on a substrate and is subsequently densified by heat treatment, for example. In this case, the initially amorphous material is converted into a crystalline or polycrystalline form. In order that the now crystalline material can be removed again from the substrate, imperfections are produced in the ceramic material, for example by ion implantation. As a result, the etching medium can more easily attack the ceramic material, so that the latter can be removed with a higher etching rate. Through inclined implantation, the method can be performed in a self-aligning manner and the ceramic material can be removed on one side, by way of example, in trenches or deep trench capacitors.

    摘要翻译： 在用于形成图案化陶瓷层的方法中，陶瓷材料沉积在基底上，并随后通过热处理致密化。 在这种情况下，最初的无定形材料被转化为结晶或多晶形式。 为了现在的结晶材料可以再次从衬底去除，例如通过离子注入在陶瓷材料中产生缺陷。 结果，蚀刻介质可以更容易地侵蚀陶瓷材料，使得后者可以以更高的蚀刻速率被去除。 通过倾斜注入，该方法可以以自对准的方式进行，并且陶瓷材料可以通过例如在沟槽或深沟槽电容器中被一侧除去。

    Selective etching to increase trench surface area
    6.
    发明授权
    Selective etching to increase trench surface area 有权
    选择性蚀刻以增加沟槽表面积

    公开(公告)号：US07157328B2

    公开(公告)日：2007-01-02

    申请号：US11047312

    申请日：2005-01-31

    申请人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

    发明人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/30604 ,  H01L29/66181

    摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

    摘要翻译： 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

    Selective etching to increase trench surface area
    7.
    发明申请
    Selective etching to increase trench surface area 有权
    选择性蚀刻以增加沟槽表面积

    公开(公告)号：US20060172486A1

    公开(公告)日：2006-08-03

    申请号：US11047312

    申请日：2005-01-31

    申请人： Helmut Tews ,  Stephan Kudelka ,  Kenneth Settlemyer

    发明人： Helmut Tews ,  Stephan Kudelka ,  Kenneth Settlemyer

    IPC分类号： H01L21/8242 ,  H01L29/94

    CPC分类号： H01L21/30604 ,  H01L29/66181

    摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

    摘要翻译： 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

    Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell
    9.
    发明申请
    Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell 失效
    用于制造具有绝缘环的沟槽电容器的方法，所述绝缘套环通过埋入触点电连接到衬底，特别是用于半导体存储器单元

    公开(公告)号：US20050026384A1

    公开(公告)日：2005-02-03

    申请号：US10901406

    申请日：2004-07-27

    申请人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sanger

    发明人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sanger

    IPC分类号： H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181

    摘要： Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

    摘要翻译： 在衬底中制造具有绝缘套环的沟槽电容器，其在一侧通过埋入触点电连接，特别地，用于具有衬底中的平面选择晶体管并通过埋入触点连接的半导体存储器单元包括提供 在硬掩模中使用开口的沟槽，在下部和中部沟槽区域中提供电容器电介质，在中央和上部沟槽区域中的套环，以及至少与绝缘套环顶部一样的导电填充物，完全用一个 填充材料，执行STI沟槽制造工艺，去除填充材料并将填充物下沉到轴环顶部以下，在轴环上方的一侧上形成绝缘区域; 露出套环上方不同侧的连接区域，并通过沉积和蚀刻金属填充物来形成掩埋触点。

    High aspect ratio PBL SiN barrier formation
    10.
    发明授权
    High aspect ratio PBL SiN barrier formation 有权
    高纵横比PBL SiN阻挡层形成

    公开(公告)号：US06677197B2

    公开(公告)日：2004-01-13

    申请号：US10032040

    申请日：2001-12-31

    申请人： Stephan Kudelka ,  Helmut Horst Tews

    发明人： Stephan Kudelka ,  Helmut Horst Tews

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L29/66181

    摘要： In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.

    摘要翻译： 在制备通常需要在瓶形成后形成套环的亚100nm研磨剂制备DT DRAM的方法中，通过形成高面积比PBL SiN阻挡层来改进提供轴环第一方案，该方法包括：a） 在SiN结点沉积和DT多晶硅填充之后的半导体结构; b）沉积多层缓冲LOCOS（PBL）Si衬垫; c）使PBL衬里氧化形成衬垫氧化物并沉积SiN阻挡层; d）沉积硅掩模 衬垫; e）使用p-掺杂剂对DT进行高定向离子注入（I / I）; f）使用SiN上的蚀刻停止对未被注入的Si的选择性湿蚀刻; g）使步骤f）的产物 在衬垫氧化物上具有蚀刻停止层的SiN湿蚀刻; h）影响衬垫氧化物上的停止的Si衬层蚀刻; i）氧化PBL Si衬垫并影响势垒SiN条; j）提供DT多晶硅填充物 进行多化学机械抛光。