公开(公告)号：US07157371B2

公开(公告)日：2007-01-02

申请号：US10653599

申请日：2003-09-02

申请人： Thomas Hecht ,  Uwe Schroeder ,  Harald Seidl ,  Martin Gutsche ,  Stefan Jakschik ,  Stephan Kudelka ,  Albert Birner

发明人： Thomas Hecht ,  Uwe Schroeder ,  Harald Seidl ,  Martin Gutsche ,  Stefan Jakschik ,  Stephan Kudelka ,  Albert Birner

IPC分类号： H01L21/44

CPC分类号： H01L27/11502 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/28061 ,  H01L21/31138 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L27/11507 ,  H01L28/57 ,  H01L29/0895 ,  H01L29/4941

摘要： A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.

摘要翻译： 由金属氧化物构成的电介质阻挡层通过在不同结构的基底衬底上的分子单层中的顺序气相沉积或分子束外延处理半导体器件的过程中以小于20纳米的厚度施加。 该方法允许间隔地从电介质材料形成有效的导电扩散阻挡层，优化阻挡层的层厚度，随后的工艺步骤的温度预算的增加以及用于去除 临时阻隔层。

公开(公告)号：US06953722B2

公开(公告)日：2005-10-11

申请号：US10425461

申请日：2003-04-29

申请人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht ,  Stefan Jakschik ,  Stephan Kudelka ,  Uwe Schröder ,  Matthias Schmeide

发明人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht ,  Stefan Jakschik ,  Stephan Kudelka ,  Uwe Schröder ,  Matthias Schmeide

IPC分类号： H01L21/311 ,  H01L21/8242

CPC分类号： H01L27/10867 ,  H01L21/31133

摘要： In a method for forming patterned ceramic layers, a ceramic material is deposited on a substrate and is subsequently densified by heat treatment, for example. In this case, the initially amorphous material is converted into a crystalline or polycrystalline form. In order that the now crystalline material can be removed again from the substrate, imperfections are produced in the ceramic material, for example by ion implantation. As a result, the etching medium can more easily attack the ceramic material, so that the latter can be removed with a higher etching rate. Through inclined implantation, the method can be performed in a self-aligning manner and the ceramic material can be removed on one side, by way of example, in trenches or deep trench capacitors.

摘要翻译： 在用于形成图案化陶瓷层的方法中，陶瓷材料沉积在基底上，并随后通过热处理致密化。 在这种情况下，最初的无定形材料被转化为结晶或多晶形式。 为了现在的结晶材料可以再次从衬底去除，例如通过离子注入在陶瓷材料中产生缺陷。 结果，蚀刻介质可以更容易地侵蚀陶瓷材料，使得后者可以以更高的蚀刻速率被去除。 通过倾斜注入，该方法可以以自对准的方式进行，并且陶瓷材料可以通过例如在沟槽或深沟槽电容器中被一侧除去。

公开(公告)号：US07176514B2

公开(公告)日：2007-02-13

申请号：US10413812

申请日：2003-04-15

申请人： Thomas Hecht ,  Albert Birner ,  Harald Seidl ,  Uwe Schröder ,  Stefan Jakschik ,  Martin Gutsche

发明人： Thomas Hecht ,  Albert Birner ,  Harald Seidl ,  Uwe Schröder ,  Stefan Jakschik ,  Martin Gutsche

IPC分类号： H01L27/108 ,  H01L21/76

CPC分类号： H01L21/02238 ,  C25D11/02 ,  C25D11/32 ,  H01L21/02258 ,  H01L21/31675 ,  H01L21/31687 ,  H01L27/1085

摘要： A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.

摘要翻译： 用于在由导电基板材料制成的基板上制造介电层的方法包括至少通过导电基板材料的自对准和自限制电化学转换为不导电的方式减少流过电介质层的缺陷的漏电流 衬底跟随材料在与缺陷相邻的衬底的部分中。 还提供了包括具有缺陷的电介质层，由导电基板材料制成的基板以及由与该缺陷相邻的部分中的非导电性基板追随材料制成的加强区域的结构。

公开(公告)号：US06919255B2

公开(公告)日：2005-07-19

申请号：US10630373

申请日：2003-07-30

申请人： Albert Birner ,  Matthias Goldbach ,  Thomas Hecht ,  Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Dirk Manger ,  Andreas Orth

发明人： Albert Birner ,  Matthias Goldbach ,  Thomas Hecht ,  Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Dirk Manger ,  Andreas Orth

IPC分类号： H01L27/108 ,  H01L21/00 ,  H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.

摘要翻译： 一种制造半导体沟槽结构的方法包括在半导体衬底中形成沟槽并用填充物填充沟槽。 具有第一最高温度的第一热处理固化填料。 从沟槽的上部区域移除填料至达边界表面限定了一个环形区域。 在具有不显着高于第一最高温度的第二最高温度的第二热处理中，衬套沉积在套环区域和边界表面上。 将衬垫从边界表面移除，从而暴露填料。 然后从沟槽的下部区域去除填料。

公开(公告)号：US20060234463A1

公开(公告)日：2006-10-19

申请号：US11399811

申请日：2006-04-07

申请人： Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

发明人： Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L28/65 ,  H01L27/1087 ,  H01L29/66181

摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.

摘要翻译： 制造诸如DRAM半导体存储器或场效应晶体管的电气部件。 制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。 为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。

公开(公告)号：US20050127421A1

公开(公告)日：2005-06-16

申请号：US10502930

申请日：2003-01-16

申请人： Harald Seidl ,  Jorn Lutzen ,  Gerhard Beitel ,  Thomas Hecht ,  Annette Sanger ,  Albert Birner

发明人： Harald Seidl ,  Jorn Lutzen ,  Gerhard Beitel ,  Thomas Hecht ,  Annette Sanger ,  Albert Birner

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/8242 ,  H01L29/51 ,  H01L27/108

CPC分类号： H01L21/28194 ,  H01L21/02175 ,  H01L21/02282 ,  H01L21/314 ,  H01L27/1085 ,  H01L27/10861 ,  H01L27/10873 ,  H01L28/40 ,  H01L29/517

摘要： A semiconductor module is described which is essentially constructed from a silicon material and has an insulation layer for example in the form of a gate insulation layer or a MOS transistor or in the form of an insulation layer of a memory cell for a dynamic memory module. The insulation layer preferably comprises a dielectric material whose band gap is greater than the band gap of SiO2. To construct the insulation layer, use is made of materials which have a metal-fluorine compound, such as e.g. lithium fluoride. Particularly thin insulation layers are provided by the material described.

摘要翻译： 描述了一种半导体模块，其基本上由硅材料构成，并且具有例如栅极绝缘层或MOS晶体管形式的绝缘层，或以动态存储器模块的存储单元的绝缘层的形式。 绝缘层优选地包括其带隙大于SiO 2带隙的电介质材料。 为了构造绝缘层，使用具有金属 - 氟化合物的材料，例如， 氟化锂。 通过所述材料提供特别薄的绝缘层。

公开(公告)号：US07531406B2

公开(公告)日：2009-05-12

申请号：US11399811

申请日：2006-04-07

申请人： Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

发明人： Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

IPC分类号： H01L21/8234

CPC分类号： H01L28/65 ,  H01L27/1087 ,  H01L29/66181

摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.

摘要翻译： 制造诸如DRAM半导体存储器或场效应晶体管的电气部件。 制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。 为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。

公开(公告)号：US20060202250A1

公开(公告)日：2006-09-14

申请号：US11076021

申请日：2005-03-10

申请人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

发明人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

IPC分类号： H01L29/94

CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L28/82

摘要： A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the counter electrode being isolated from the storage electrode by the dielectric layer, wherein the storage electrode is formed as a body which is delimited by at least one curved surface having a center of curvature outside the body in a plane parallel to the substrate surface. According to another configuration, the storage electrode is formed as a body which is delimited by at least one set having two contiguous planes, the two planes extending perpendicularly with respect to the substrate surface, a point of intersection of normals of the two planes lying outside the body.

摘要翻译： 适用于DRAM单元的存储电容器至少部分地形成在衬底表面之上，并且包括：至少部分地形成在衬底表面上方的存储电极，与存储电极相邻形成的电介质层和形成的对电极 所述对置电极通过所述电介质层与所述存储电极隔离，其中所述存储电极形成为主体，所述主体由平行于所述电介质层的平面中的具有在所述主体外部的曲率中心的至少一个曲面限定 基材表面。 根据另一种结构，存储电极形成为由具有两个相邻平面的至少一组限定的主体，两个平面相对于基板表面垂直延伸，两个平面的法线相交点位于外部 身体。

公开(公告)号：US06693016B2

公开(公告)日：2004-02-17

申请号：US10233690

申请日：2002-09-03

申请人： Martin Gutsche ,  Thomas Hecht ,  Matthias Leonhardt ,  Uwe Schröder ,  Harald Seidl

发明人： Martin Gutsche ,  Thomas Hecht ,  Matthias Leonhardt ,  Uwe Schröder ,  Harald Seidl

IPC分类号： H01L2120

CPC分类号： H01L27/10861

摘要： The novel trench capacitors have a constant or increased capacitance. Materials for a second electrode region and if appropriate a first electrode region include a metallic material, a metal nitride, or the like, and/or a dielectric region is formed with a material with an increased dielectric constant. An insulation region is formed in the upper wall region of the trench after the first electrode region or the second electrode region has been formed, by selective and local oxidation.

摘要翻译： 新颖的沟槽电容器具有恒定或增加的电容。 第二电极区域的材料和适当的第一电极区域包括金属材料，金属氮化物等，和/或介电区域由介电常数增加的材料形成。 通过选择性和局部氧化，在形成第一电极区域或第二电极区域之后，在沟槽的上壁区域中形成绝缘区域。

公开(公告)号：US20060264054A1

公开(公告)日：2006-11-23

申请号：US11100325

申请日：2005-04-06

申请人： Martin Gutsche ,  Thomas Hecht ,  Harald Seidl ,  Uwe Rudolph ,  Barbara Lorenz ,  Elisabeth Weikmann

发明人： Martin Gutsche ,  Thomas Hecht ,  Harald Seidl ,  Uwe Rudolph ,  Barbara Lorenz ,  Elisabeth Weikmann

IPC分类号： H01L21/465

CPC分类号： H01L21/30655 ,  H01L21/743 ,  H01L21/76898

摘要： The present invention relates to a method for etching a trench in a semiconductor substrate. More specifically, the present invention relates to a method for etching deep trenches such as those having aspect ratios of 30 and higher. According to embodiments of the invention, a method for etching a trench in a semiconductor substrate includes a first etch cycle wherein the trench is etched to a first depth. Thereafter, a protective liner is deposited on at least the upper part of the trench's sidewalls. The protective liner includes inorganic material. During at least one second etch cycle, the trench is etched to its final depth.

摘要翻译： 本发明涉及一种用于蚀刻半导体衬底中的沟槽的方法。 更具体地说，本发明涉及一种蚀刻深沟槽的方法，例如具有30或更高的纵横比的那些。 根据本发明的实施例，用于蚀刻半导体衬底中的沟槽的方法包括第一蚀刻循环，其中沟槽被蚀刻到第一深度。 此后，保护性衬垫至少沉积在沟槽侧壁的上部。 保护性衬垫包括无机材料。 在至少一个第二蚀刻周期期间，将沟槽蚀刻到其最终深度。