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公开(公告)号：US06539025B1
公开(公告)日：2003-03-25
申请号：US09268500
申请日：1999-03-11
IPC分类号： H04L1228
CPC分类号： H04L47/18 , G06F15/17375 , H04J3/0682 , H04J3/0685 , H04L7/046 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L12/64 , H04L12/6402 , H04L41/00 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/15 , H04L47/16 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/50 , H04L47/52 , H04L47/521 , H04L47/522 , H04L47/525 , H04L47/56 , H04L47/621 , H04L47/6215 , H04L47/6225 , H04L47/627 , H04L47/70 , H04L47/722 , H04L47/743 , H04L47/745 , H04L47/762 , H04L47/782 , H04L47/805 , H04L47/822 , H04L49/101 , H04L49/103 , H04L49/106 , H04L49/107 , H04L49/108 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/20 , H04L49/201 , H04L49/203 , H04L49/205 , H04L49/25 , H04L49/253 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/503 , H04L49/505 , H04L49/506 , H04L49/508 , H04L49/55 , H04L49/552 , H04L49/555 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9078 , H04L69/32 , H04L69/324 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5684 , H04L2012/5685 , H04Q11/0478 , H04W28/14 , Y10S370/902 , Y10S370/905
摘要： An Asynchronous Transfer Mode switch and method which facilitate priority arbitration of point-to-point and point-to-multipoint transmission are disclosed. To execute point-to-multipoint operation a bandwidth arbiter maintains a first list of connections and bit vectors indicating designated destination ports. The list maintained by the bandwidth arbiter is then compared to an unassigned output port bit vector to determine matches therebetween at which point-to-multipoint transmission may be made by utilizing instantaneously unused bandwidth within the switch. To execute point-to-point operation each input port maintains a list of connections associated with each output port, and those lists are used in conjunction with output port request information per input port in the bandwidth arbiter to match requests to the unassigned output port bit vector. The bandwidth arbiter may also assign priority to connections in the list.
摘要翻译： 公开了一种促进点对点和点对多点传输的优先仲裁的异步传输模式切换和方法。 为了执行点对多点操作，带宽仲裁器维护指示指定的目的地端口的连接的第一列表和位向量。 然后将由带宽仲裁器维护的列表与未分配的输出端口比特向量进行比较，以确定它们之间的匹配，可以通过利用交换机内的瞬时未使用的带宽进行点对多点传输。 为了执行点对点操作，每个输入端口维护与每个输出端口相关联的连接列表，并且这些列表与带宽仲裁器中每个输入端口的输出端口请求信息一起使用，以将请求匹配到未分配的输出端口位 向量。 带宽仲裁器还可以为列表中的连接分配优先级。
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公开(公告)号：US06236655B1
公开(公告)日：2001-05-22
申请号：US08685194
申请日：1996-07-18
IPC分类号： H04L1228
CPC分类号： H04L47/18 , G06F15/17375 , H04J3/0682 , H04J3/0685 , H04L7/046 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L12/64 , H04L12/6402 , H04L41/00 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/15 , H04L47/16 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/50 , H04L47/52 , H04L47/521 , H04L47/522 , H04L47/525 , H04L47/56 , H04L47/621 , H04L47/6215 , H04L47/6225 , H04L47/627 , H04L47/70 , H04L47/722 , H04L47/743 , H04L47/745 , H04L47/762 , H04L47/782 , H04L47/805 , H04L47/822 , H04L49/101 , H04L49/103 , H04L49/106 , H04L49/107 , H04L49/108 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/20 , H04L49/201 , H04L49/203 , H04L49/205 , H04L49/25 , H04L49/253 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/503 , H04L49/505 , H04L49/506 , H04L49/508 , H04L49/55 , H04L49/552 , H04L49/555 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9078 , H04L69/32 , H04L69/324 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5684 , H04L2012/5685 , H04Q11/0478 , H04W28/14 , Y10S370/902 , Y10S370/905
摘要： A system (10) is provided for identifying a processing port (12) and a link (22) at which a cell (24) is received. The system (10) includes a logical link table (14) having a plurality of logical link entries (30). Each logical link entry (30), which corresponds to a particular link (22) of a processing port (12) associated with the logical link table (14), specifies a numerical value. The processing port (12) may receive the cell (24) at one of a plurality of links (22). The processing port (12) can convert the cell (24) by replacing a numerical value of an identification field, such as a virtual channel identification field (28), of the cell (24) with the numerical value specified by the logical link entry (30) corresponding to the link (22) at which the cell (24) is received. A switch control module (18), which is connected to the processing port (12), may receive the converted cell (38). The switch control module (18) can identify the link (22) and the processing port (12) at which the cell (24) corresponding to the converted cell (38) was received by referencing a reverse mapping table (20) using the numerical value of the logical link entry (30) in the converted cell (38).
摘要翻译： 提供了一种用于识别接收单元（24）的处理端口（12）和链路（22）的系统（10）。 系统（10）包括具有多个逻辑链路条目（30）的逻辑链路表（14）。 对应于与逻辑链接表（14）相关联的处理端口（12）的特定链路（22）的每个逻辑链接条目（30）指定数值。 处理端口（12）可以在多个链路（22）中的一个链路（22）处接收小区（24）。 处理端口（12）可以通过用逻辑链路条目指定的数值替换小区（24）的标识字段（诸如虚拟信道标识字段（28））的数值，从而转换小区（24） （30）对应于接收所述单元（24）的链路（22）。 连接到处理端口（12）的开关控制模块（18）可以接收转换的单元（38）。 切换控制模块（18）可以通过参照反向映射表（20）来识别通过参照反向映射表（20）来接收与转换的小区（38）相对应的小区（24）的链路（22）和处理端口（12） 转换单元（38）中的逻辑链接条目（30）的值。
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公开(公告)号：US5982776A
公开(公告)日：1999-11-09
申请号：US827931
申请日：1997-04-29
IPC分类号： G06F12/02 , G06F9/46 , G06F15/173 , H04J3/06 , H04L1/22 , H04L7/04 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/56 , H04L12/64 , H04L13/08 , H04L29/06 , H04L29/08 , H04M3/00 , H04M3/08 , H04M3/22 , H04Q3/00 , H04Q3/545 , H04Q11/04
CPC分类号： H04L47/18 , G06F15/17375 , H04L12/24 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L12/5693 , H04L12/5695 , H04L12/64 , H04L12/6402 , H04L41/00 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/15 , H04L47/16 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/52 , H04L47/521 , H04L47/522 , H04L47/525 , H04L47/56 , H04L47/621 , H04L47/6215 , H04L47/6225 , H04L47/627 , H04L47/722 , H04L47/743 , H04L47/745 , H04L47/762 , H04L47/782 , H04L47/805 , H04L47/822 , H04L49/101 , H04L49/103 , H04L49/106 , H04L49/107 , H04L49/108 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/20 , H04L49/203 , H04L49/205 , H04L49/253 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/503 , H04L49/505 , H04L49/506 , H04L49/552 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9078 , H04L69/32 , H04L69/324 , H04Q11/0478 , H04W28/14 , H04J3/0682 , H04J3/0685 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5684 , H04L2012/5685 , H04L49/201 , H04L49/25 , H04L49/508 , H04L49/55 , H04L49/555 , H04L7/046 , Y10S370/902 , Y10S370/905
摘要： An apparatus and a method are disclosed for arbitrating between streams of ATM cells, or sources for a connection, on multiple input port processors vying for an opportunity to be transmitted as a fixed bandwidth, or allocated, connection on a single output port through a network switch. The network switch maintains a plurality of input port processors, at least one output port, and input and output buffers associated with the respective input and output ports. Streams of ATM cells enter the network switch as sources for a connection through the multiple input port processors and are buffered in the input buffers. The ATM cells are then routed from the input buffers to an output buffer in the output port. The network switch also provides a multipoint topology controller (MTC) and a bandwidth arbiter (BA) for performing the arbitration.
摘要翻译： 公开了一种装置和方法，用于在多个输入端口处理器上的ATM信元流或连接源之间进行仲裁，以争取通过网络在单个输出端口上作为固定带宽传输的机会或分配的连接 开关。 网络交换机维护多个输入端口处理器，至少一个输出端口以及与各个输入和输出端口相关联的输入和输出缓冲器。 ATM信元的流进入网络交换机作为通过多个输入端口处理器进行连接的源，并被缓冲在输入缓冲器中。 然后将ATM信元从输入缓冲器路由到输出端口中的输出缓冲器。 网络交换机还提供用于执行仲裁的多点拓扑控制器（MTC）和带宽仲裁器（BA）。
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公开(公告)号：US5933429A
公开(公告)日：1999-08-03
申请号：US827932
申请日：1997-04-29
申请人： Richard G. Bubenik , Stephen A. Caldara , Stephen A. Hauser , Thomas A. Manning , Stephen R. Veit
发明人： Richard G. Bubenik , Stephen A. Caldara , Stephen A. Hauser , Thomas A. Manning , Stephen R. Veit
IPC分类号： G06F12/02 , G06F9/46 , G06F15/173 , H04J3/06 , H04L1/22 , H04L7/04 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/56 , H04L12/64 , H04L13/08 , H04L29/06 , H04L29/08 , H04M3/00 , H04M3/08 , H04M3/22 , H04Q3/00 , H04Q3/545 , H04Q11/04
CPC分类号： H04L47/18 , G06F15/17375 , H04L12/24 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L12/5693 , H04L12/5695 , H04L12/64 , H04L12/6402 , H04L41/00 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/15 , H04L47/16 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/52 , H04L47/521 , H04L47/522 , H04L47/525 , H04L47/56 , H04L47/621 , H04L47/6215 , H04L47/6225 , H04L47/627 , H04L47/722 , H04L47/743 , H04L47/745 , H04L47/762 , H04L47/782 , H04L47/805 , H04L47/822 , H04L49/101 , H04L49/103 , H04L49/106 , H04L49/107 , H04L49/108 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/20 , H04L49/203 , H04L49/205 , H04L49/253 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/503 , H04L49/505 , H04L49/506 , H04L49/552 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9078 , H04L69/32 , H04L69/324 , H04Q11/0478 , H04W28/14 , H04J3/0682 , H04J3/0685 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5684 , H04L2012/5685 , H04L49/201 , H04L49/25 , H04L49/508 , H04L49/55 , H04L49/555 , H04L7/046 , Y10S370/902 , Y10S370/905
摘要： An apparatus and a method are disclosed for unencumbering valuable switching resources in a network switch involved in a multipoint-to-multipoint switching scenario. The network switch includes an input processing port that is connected to a plurality of input links, and an output processing port that is connected to a plurality of output links. A data cell received on an input link is processed by the input processing port by appending a link number, a port number, and a connection identification code associated with the input processing port to the data cell. The data cell is then transferred to the output processing port where it is processed by comparing the appended link number, port number, and connection identification code with those associated with the output processing port. The data cell is then stored in a data buffering queue in the output processing port according to a matching scheme.
摘要翻译： 公开了一种用于在涉及多点到多点交换场景的网络交换机中对有价值的交换资源进行编号的装置和方法。 网络交换机包括连接到多个输入链路的输入处理端口和连接到多个输出链路的输出处理端口。 通过将与输入处理端口相关联的链接号，端口号和连接识别码附加到数据单元，由输入处理端口处理在输入链路上接收的数据信元。 然后通过将附加的链路号，端口号和连接识别码与与输出处理端口相关联的号码进行比较，将数据信元传送到输出处理端口。 然后根据匹配方案将数据单元存储在输出处理端口中的数据缓冲队列中。
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公开(公告)号：US5905729A
公开(公告)日：1999-05-18
申请号：US685196
申请日：1996-07-18
申请人： Michael E. Gaddis , Richard G. Bubenik , Stephen A. Caldara , Stephen A. Hauser , Thomas A. Manning
发明人： Michael E. Gaddis , Richard G. Bubenik , Stephen A. Caldara , Stephen A. Hauser , Thomas A. Manning
IPC分类号： G06F12/02 , G06F9/46 , G06F15/173 , H04J3/06 , H04L1/22 , H04L7/04 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/56 , H04L12/64 , H04L13/08 , H04L29/06 , H04L29/08 , H04M3/00 , H04M3/08 , H04M3/22 , H04Q3/00 , H04Q3/545 , H04Q11/04 , H04J3/12
CPC分类号： H04L47/18 , G06F15/17375 , H04L12/24 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L12/5693 , H04L12/5695 , H04L12/64 , H04L12/6402 , H04L41/00 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/15 , H04L47/16 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/52 , H04L47/521 , H04L47/522 , H04L47/525 , H04L47/56 , H04L47/621 , H04L47/6215 , H04L47/6225 , H04L47/627 , H04L47/722 , H04L47/743 , H04L47/745 , H04L47/762 , H04L47/782 , H04L47/805 , H04L47/822 , H04L49/101 , H04L49/103 , H04L49/106 , H04L49/107 , H04L49/108 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/20 , H04L49/203 , H04L49/205 , H04L49/253 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/503 , H04L49/505 , H04L49/506 , H04L49/552 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9078 , H04L69/32 , H04L69/324 , H04Q11/0478 , H04W28/14 , H04J3/0682 , H04J3/0685 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5684 , H04L2012/5685 , H04L49/201 , H04L49/25 , H04L49/508 , H04L49/55 , H04L49/555 , H04L7/046 , Y10S370/902 , Y10S370/905
摘要： A system (10) is provided for mapping a data cell (32) in a communication switch. The system (10) includes a virtual translation table (40) having at least one virtual path translation table queue entry (92) and at least one virtual channel translation table queue entry (90). A to-switch port processor (12), which can access the virtual translation table (40), has at least one link (16-30) which receives the data cell (32). The to-switch port processor (12) maps the received data cell (32) to a queue descriptor using the virtual translation table (40).
摘要翻译： 提供了一种用于映射通信交换机中的数据信元（32）的系统（10）。 系统（10）包括具有至少一个虚拟路径转换表队列条目（92）和至少一个虚拟通道转换表队列条目（90）的虚拟转换表（40）。 可以访问虚拟转换表（40）的交换机端口处理器（12）具有接收数据信元（32）的至少一个链路（16-30）。 交换机端口处理器（12）使用虚拟转换表（40）将接收到的数据单元（32）映射到队列描述符。
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公开(公告)号：US06426957B1
公开(公告)日：2002-07-30
申请号：US09209526
申请日：1998-12-11
IPC分类号： H04L1228
CPC分类号： H04L47/18 , G06F15/17375 , H04J3/0682 , H04J3/0685 , H04L7/046 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L12/64 , H04L12/6402 , H04L41/00 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/15 , H04L47/16 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/50 , H04L47/52 , H04L47/521 , H04L47/522 , H04L47/525 , H04L47/56 , H04L47/621 , H04L47/6215 , H04L47/6225 , H04L47/627 , H04L47/70 , H04L47/722 , H04L47/743 , H04L47/745 , H04L47/762 , H04L47/782 , H04L47/805 , H04L47/822 , H04L49/101 , H04L49/103 , H04L49/106 , H04L49/107 , H04L49/108 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/20 , H04L49/201 , H04L49/203 , H04L49/205 , H04L49/25 , H04L49/253 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/503 , H04L49/505 , H04L49/506 , H04L49/508 , H04L49/55 , H04L49/552 , H04L49/555 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9078 , H04L69/32 , H04L69/324 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5684 , H04L2012/5685 , H04Q11/0478 , H04W28/14 , Y10S370/902 , Y10S370/905
摘要： An asynchronous transfer mode (ATM) based service consolidation switch (10) includes an input/output module (22) having a to-switch port (TSPP) processor (90) and a from-switch port processor (FSPP) (92). The TSPP (90) and the FSPP (92) communicate with a bandwidth arbiter (114), multipoint topology controllers (116), and a data crossbar (117) on a switch control module (32). The TSPP (90) receives traffic over links for conversion into an internal cell format. Internal cells are buffered until allowed to transfer to an appropriate FSPP (92). Multipoint topology controllers (116) performs translations for internal switch flow control through interactions between the TSPPs (90), FSPPs (92), and the bandwidth arbiter (114). The bandwidth arbiter (114) performs appropriate bandwidth arbitration to allow internal cells to flow from TSPPs (90) to FSPPs (92) over the data crossbar (117).
摘要翻译： 基于异步传输模式（ATM）的服务合并开关（10）包括具有交换机端口（TSPP）处理器（90）和从交换机端口处理器（FSPP）（92））的输入/输出模块（22）。 TSPP（90）和FSPP（92）与开关控制模块（32）上的带宽仲裁器（114），多点拓扑控制器（116）和数据交叉开关（117）通信。 TSPP（90）通过链路接收流量以转换为内部小区格式。 内部细胞被缓冲直到允许转移到适当的FSPP（92）。 多点拓扑控制器（116）通过TSPP（90），FSPP（92）和带宽仲裁器（114）之间的交互来执行用于内部交换机流控制的转换。 带宽仲裁器（114）执行适当的带宽仲裁以允许内部小区从数据交叉开关（117）从TSPP（90）流向FSPP（92）。
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公开(公告)号：US6141346A
公开(公告)日：2000-10-31
申请号：US683131
申请日：1996-07-18
IPC分类号： G06F12/02 , G06F9/46 , G06F15/173 , H04J3/06 , H04L1/22 , H04L7/04 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/56 , H04L12/64 , H04L13/08 , H04L29/06 , H04L29/08 , H04M3/00 , H04M3/08 , H04M3/22 , H04Q3/00 , H04Q3/545 , H04Q11/04 , H04L12/00
CPC分类号： H04L47/18 , G06F15/17375 , H04L12/24 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L12/5693 , H04L12/5695 , H04L12/64 , H04L12/6402 , H04L41/00 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/15 , H04L47/16 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/52 , H04L47/521 , H04L47/522 , H04L47/525 , H04L47/56 , H04L47/621 , H04L47/6215 , H04L47/6225 , H04L47/627 , H04L47/722 , H04L47/743 , H04L47/745 , H04L47/762 , H04L47/782 , H04L47/805 , H04L47/822 , H04L49/101 , H04L49/103 , H04L49/106 , H04L49/107 , H04L49/108 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/20 , H04L49/203 , H04L49/205 , H04L49/253 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/503 , H04L49/505 , H04L49/506 , H04L49/552 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9078 , H04L69/32 , H04L69/324 , H04Q11/0478 , H04W28/14 , H04J3/0682 , H04J3/0685 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5684 , H04L2012/5685 , H04L49/201 , H04L49/25 , H04L49/508 , H04L49/55 , H04L49/555 , H04L7/046 , Y10S370/902 , Y10S370/905
摘要： An Asynchronous Transfer Mode switch and method which facilitate point-to-multipoint transmission are disclosed. Each input port within the switch includes a switch allocation table ("SAT") which manages bandwidth allocation and delay. Each SAT includes a plurality of sequentially ordered cell time slots, a subqueue and a synchronized pointer which is directed to one of the slots such that at any given point in time each of the pointers is directed to the same slot location in the respective SAT with which the pointer is associated. To execute point-to-multipoint operation where output port conflicts are present the switch transmits copies of the cell to the output ports at different points in time. More particularly, the switch transmits copies of the cell to available output ports, and tracks such transmission for managing future transmission to unserviced output ports. To track transmission the switch includes a map and scoreboard. The subqueues are used to index into a table and may be associated with one or more output ports. The map indicates which subqueues, and hence which output ports, are initially eligible to receive a copy of the cell. The scoreboard indicates which subqueues, and hence which output ports, have received a copy of the cell. Tracking is realized by updating the scoreboard when copies of cells are transmitted. Copies of the cell are not sent to already serviced output ports. When each designated subqueue has been service, and hence each associated output port has been serviced, the cell is dequeued.
摘要翻译： 公开了一种促进点对多点传输的异步传输模式开关和方法。 交换机内的每个输入端口包括管理带宽分配和延迟的交换机分配表（“SAT”）。 每个SAT包括多个顺序排序的单元时隙，一个子队列和一个同步的指针，该指针指向一个时隙，使得在任何给定的时间点，每个指针指向相应的SAT中的相同的时隙位置， 指针相关联。 为了执行出现输出端口冲突的点对多点操作，交换机将不同时间点的单元的副本传送到输出端口。 更具体地，交换机将小区的副本传送到可用的输出端口，并且跟踪这样的传输，以将未来的传输管理到未服务的输出端口。 为了跟踪传输，交换机包括地图和记分牌。 子队列用于索引到表中，并且可以与一个或多个输出端口相关联。 地图指示哪些子队列，因此哪些输出端口最初有资格接收单元的副本。 记分板指示哪个子队列，从而哪个输出端口已经接收到该单元的副本。 跟踪是通过在传送单元的副本时更新记分板来实现的。 单元的副本不会发送到已服务的输出端口。 当每个指定的子队列已经被服务，并且因此每个关联的输出端口已被服务时，该单元出队。
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8.发明授权Network switch utilizing centralized and partitioned memory for connection topology information storage 失效网络交换机利用集中式和分区式存储器连接拓扑信息存储
公开(公告)号：US5917805A
公开(公告)日：1999-06-29
申请号：US685240
申请日：1996-07-18
IPC分类号： G06F12/02 , G06F9/46 , G06F15/173 , H04J3/06 , H04L1/22 , H04L7/04 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/56 , H04L12/64 , H04L13/08 , H04L29/06 , H04L29/08 , H04M3/00 , H04M3/08 , H04M3/22 , H04Q3/00 , H04Q3/545 , H04Q11/04
CPC分类号： H04L47/18 , G06F15/17375 , H04L12/24 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L12/5693 , H04L12/5695 , H04L12/64 , H04L12/6402 , H04L41/00 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/15 , H04L47/16 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/52 , H04L47/521 , H04L47/522 , H04L47/525 , H04L47/56 , H04L47/621 , H04L47/6215 , H04L47/6225 , H04L47/627 , H04L47/722 , H04L47/743 , H04L47/745 , H04L47/762 , H04L47/782 , H04L47/805 , H04L47/822 , H04L49/101 , H04L49/103 , H04L49/106 , H04L49/107 , H04L49/108 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/20 , H04L49/203 , H04L49/205 , H04L49/253 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/503 , H04L49/505 , H04L49/506 , H04L49/552 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9078 , H04L69/32 , H04L69/324 , H04Q11/0478 , H04W28/14 , H04J3/0682 , H04J3/0685 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5684 , H04L2012/5685 , H04L49/201 , H04L49/25 , H04L49/508 , H04L49/55 , H04L49/555 , H04L7/046 , Y10S370/902 , Y10S370/905
摘要： A network switch utilizing centralized and partitioned memory for storing connection topology information. The switch includes at least one input port, at least one output port and a central switch fabric interconnecting the input port and output port, with the connection topology memory centralized at the switch fabric. The central switch fabric includes at least one input side translator associated with a predetermined number of input ports and at least one output side translator associated with a predetermined number of output ports. The connection topology memory is distributed among the at least one input side translator and the at least one output side translator. With this arrangement, memory bandwidth requirements associated with connection topology look-up operations are distributed and scaling the number of ports is facilitated.
摘要翻译： 一种网络交换机，利用集中分区的存储器来存储连接拓扑信息。 交换机包括至少一个输入端口，至少一个输出端口和互连输入端口和输出端口的中央交换机结构，连接拓扑存储器集中在交换结构处。 中央交换结构包括与预定数量的输入端口相关联的至少一个输入侧转换器和与预定数量的输出端口相关联的至少一个输出侧转换器。 连接拓扑存储器分布在至少一个输入侧转换器和至少一个输出侧转换器中。 通过这种安排，与连接拓扑查找操作相关联的存储器带宽需求被分配并且缩短了端口数量。
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9.发明授权
公开(公告)号：US5872769A
公开(公告)日：1999-02-16
申请号：US683447
申请日：1996-07-18
IPC分类号： G06F12/02 , G06F9/46 , G06F15/173 , H04J3/06 , H04L1/22 , H04L7/04 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/56 , H04L12/64 , H04L13/08 , H04L29/06 , H04L29/08 , H04M3/00 , H04M3/08 , H04M3/22 , H04Q3/00 , H04Q3/545 , H04Q11/04
CPC分类号： H04L47/18 , G06F15/17375 , H04L12/24 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L12/5693 , H04L12/5695 , H04L12/64 , H04L12/6402 , H04L41/00 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/15 , H04L47/16 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/52 , H04L47/521 , H04L47/522 , H04L47/525 , H04L47/56 , H04L47/621 , H04L47/6215 , H04L47/6225 , H04L47/627 , H04L47/722 , H04L47/743 , H04L47/745 , H04L47/762 , H04L47/782 , H04L47/805 , H04L47/822 , H04L49/101 , H04L49/103 , H04L49/106 , H04L49/107 , H04L49/108 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/20 , H04L49/203 , H04L49/205 , H04L49/253 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/503 , H04L49/505 , H04L49/506 , H04L49/552 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9078 , H04L69/32 , H04L69/324 , H04Q11/0478 , H04W28/14 , H04J3/0682 , H04J3/0685 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5684 , H04L2012/5685 , H04L49/201 , H04L49/25 , H04L49/508 , H04L49/55 , H04L49/555 , H04L7/046 , Y10S370/902 , Y10S370/905
摘要： A linked-list structure and method for use in an ATM network switch capable of adaptively providing highly efficient, and thus low cost, integrated services therein. The linked-list structure involves the creation of a list having pointers to a subsequent linked list as list entries. Within the subsequent linked list, each entry can be a pointer to a further linked list. The structure can be expanded to further levels of linked lists as required. Bandwidth distribution is thus achieved among list members at each level. The linked-list structure is employed in the present switch, which includes an input port processor, a bandwidth arbiter, and an output port processor, for switch bandwidth scheduling for both point-to-point, multipoint-to-point and point-to-multipoint cell transfers from the input port processor, and for output link scheduling at the output port processor.
摘要翻译： 一种在ATM网络交换机中使用的链路列表结构和方法，其能够自适应地提供其中高效且因此低成本的综合业务。 链表结构涉及创建具有作为列表条目的后续链接列表的指针的列表。 在随后的链表中，每个条目可以是指向另一个链表的指针。 可以根据需要将结构扩展到更多级别的链表。 因此，在每个级别的列表成员之间实现带宽分配。 在本交换机中采用链表结构，其包括输入端口处理器，带宽仲裁器和输出端口处理器，用于点到点，多点到点和点对点的交换带宽调度 从输入端口处理器传输多重单元，并在输出端口处理器输出链路调度。
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公开(公告)号：US5862137A
公开(公告)日：1999-01-19
申请号：US683333
申请日：1996-07-18
IPC分类号： G06F12/02 , G06F9/46 , G06F15/173 , H04J3/06 , H04L1/22 , H04L7/04 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/56 , H04L12/64 , H04L13/08 , H04L29/06 , H04L29/08 , H04M3/00 , H04M3/08 , H04M3/22 , H04Q3/00 , H04Q3/545 , H04Q11/04
CPC分类号： H04L47/18 , G06F15/17375 , H04L12/24 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L12/5693 , H04L12/5695 , H04L12/64 , H04L12/6402 , H04L41/00 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/15 , H04L47/16 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/52 , H04L47/521 , H04L47/522 , H04L47/525 , H04L47/56 , H04L47/621 , H04L47/6215 , H04L47/6225 , H04L47/627 , H04L47/722 , H04L47/743 , H04L47/745 , H04L47/762 , H04L47/782 , H04L47/805 , H04L47/822 , H04L49/101 , H04L49/103 , H04L49/106 , H04L49/107 , H04L49/108 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/20 , H04L49/203 , H04L49/205 , H04L49/253 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/503 , H04L49/505 , H04L49/506 , H04L49/552 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9078 , H04L69/32 , H04L69/324 , H04Q11/0478 , H04W28/14 , H04J3/0682 , H04J3/0685 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5684 , H04L2012/5685 , H04L49/201 , H04L49/25 , H04L49/508 , H04L49/55 , H04L49/555 , H04L7/046 , Y10S370/902 , Y10S370/905
摘要： An Asynchronous Transfer Mode switch and method which facilitate point-to-multipoint transmission are disclosed. The switch includes a bandwidth arbiter, and each input port within the switch includes a switch allocation table ("SAT") which controls bandwidth allocation between input and output ports. Each SAT includes a plurality of sequentially ordered cell time slots and a synchronized pointer which is directed to one of the slots such that at any given point in time each of the pointers is directed to the same slot location in the respective SAT with which the pointer is associated. To execute point-to-multipoint operation the bandwidth arbiter maintains a list of connections and bit vectors indicating the designated destination ports for a point-to-multipoint cell. The list maintained by the bandwidth arbiter is then compared to an unassigned output port bit vector generated from the SATs to determine matches therebetween, at which point-to-multipoint transmission may be made by utilizing instantaneously unused bandwidth within the switch while arbitration distributes bandwidth among competing point-to-multipoint connections. The bandwidth arbiter may also assign priority to connections in the list.
摘要翻译： 公开了一种促进点对多点传输的异步传输模式开关和方法。 交换机包括带宽仲裁器，并且交换机内的每个输入端口包括控制输入和输出端口之间的带宽分配的交换机分配表（“SAT”）。 每个SAT包括多个顺序排序的单元时隙和指向这些时隙中的一个的同步指针，使得在任何给定的时间点，每个指针指向相应的SAT中的相同的时隙位置，与该指针 已关联的。 为了执行点对多点操作，带宽仲裁器维护指示用于点对多点小区的指定目的地端口的连接列表和位向量。 然后将由带宽仲裁器维护的列表与从SAT产生的未分配的输出端口比特向量进行比较，以确定它们之间的匹配，在该点处可以通过利用交换机内的瞬时未使用的带宽来进行点对多点传输，同时仲裁分配带宽 竞争点对多点连接。 带宽仲裁器还可以为列表中的连接分配优先级。
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