Method and apparatus for loosely synchronizing closed free running raster displays
    1.
    发明授权
    Method and apparatus for loosely synchronizing closed free running raster displays 失效
    松动地同步封闭自由运行的光栅显示器的方法和装置

    公开(公告)号:US06195086B1

    公开(公告)日:2001-02-27

    申请号:US08996786

    申请日:1997-12-23

    CPC classification number: H04N5/073 G09G5/12 G09G2310/0224 H04N5/04 H04N7/012

    Abstract: The present invention is a means and method for synchronizing closed free-running systems, such as graphics systems, with no external synchronization signals required. Video games and most computer display controllers are closed free-running systems. Because most such systems have the means to switch between an interlaced and non-interlaced operation, and because interlaced and non-interlaced modes have a relative timing variation, the timing between two or more such closed free-running systems can be synchronized. This method allows synchronization with an imprecise timing reference. The vertical display timing is the free-running oscillator and the interlaced/non-interlaced mode transition is used as the timing adjustment means. The actual arrival time of data in a communication medium connecting two systems being synchronized is used in relation to an expected arrival time to provide the clock reference.

    Abstract translation: 本发明是用于使没有外部同步信号所需的诸如图形系统的闭合自由运行系统同步的方法和方法。 视频游戏和大多数计算机显示控制器是封闭的自由运行系统。 因为大多数这样的系统具有在隔行扫描和非隔行扫描操作之间切换的手段,并且由于隔行扫描和非隔行扫描模式具有相对定时变化,所以两个或更多个这样的关闭自由运行系统之间的时序可以被同步。 该方法允许与不准确的定时参考同步。 垂直显示定时是自由运行的振荡器,并且使用隔行/非隔行扫描模式转换作为定时调整装置。 数据在连接正在同步的两个系统的通信介质中的实际到达时间与预期到达时间有关,以提供时钟参考。

    Method and apparatus for loosely sychronizing closed free-running raster
displays
    2.
    发明授权
    Method and apparatus for loosely sychronizing closed free-running raster displays 失效
    松动地同步闭合的自由运行光栅显示的方法和装置

    公开(公告)号:US5790113A

    公开(公告)日:1998-08-04

    申请号:US713593

    申请日:1996-09-12

    CPC classification number: G09G5/12 H04N5/073 H04N7/01 G09G2310/0224

    Abstract: The present invention is a means and method for synchronizing closed free-running systems, such as graphics systems, with no external synchronization signals required. Video games and most computer display controllers are closed free-running systems. Because most such systems have the means to switch between an interlaced and non-interlaced operation, and because interlaced and non-interlaced modes have a relative timing variation, the timing between two or more such closed free-running systems can be synchronized. This method allows synchronization with an imprecise timing reference. The vertical display timing is the free-running oscillator and the interlaced/non-interlaced mode transition is used as the timing adjustment means. The actual arrival time of data in a communication medium connecting two systems being synchronized is used in relation to an expected arrival time to provide the clock reference.

    Abstract translation: 本发明是用于使没有外部同步信号所需的诸如图形系统的闭合自由运行系统同步的方法和方法。 视频游戏和大多数计算机显示控制器是封闭的自由运行系统。 因为大多数这样的系统具有在隔行扫描和非隔行扫描操作之间切换的手段,并且由于隔行扫描和非隔行扫描模式具有相对定时变化,所以两个或更多个这样的关闭自由运行系统之间的时序可以被同步。 该方法允许与不准确的定时参考同步。 垂直显示定时是自由运行的振荡器,并且使用隔行/非隔行扫描模式转换作为定时调整装置。 数据在连接正在同步的两个系统的通信介质中的实际到达时间与预期到达时间有关,以提供时钟参考。

    Method and apparatus for synchronizing the execution of multiple video
game systems in a networked environment
    3.
    发明授权
    Method and apparatus for synchronizing the execution of multiple video game systems in a networked environment 失效
    用于在网络环境中同步多个视频游戏系统的执行的方法和装置

    公开(公告)号:US5775996A

    公开(公告)日:1998-07-07

    申请号:US704930

    申请日:1996-08-28

    Abstract: The present invention is a means and method for synchronizing the execution of multiple video game systems in a networked environment with no external synchronization signals required. Video games and most computer display controllers are closed free-running systems. Because most such systems have the means to switch between an interlaced and non-interlaced operation, and because interlaced and non-interlaced modes have a relative timing variation, the timing between two or more such closed free-running systems can be synchronized. This method allows synchronization with an imprecise timing reference. The vertical display timing is the free-running oscillator and the interlaced/non-interlaced mode transition is used as the timing adjustment means. The actual arrival time of data in a communication medium connecting two systems being synchronized is used in relation to an expected arrival time to provide the clock reference.

    Abstract translation: 本发明是一种用于在网络环境中同步多个视频游戏系统的执行而不需要外部同步信号的方法和方法。 视频游戏和大多数计算机显示控制器是封闭的自由运行系统。 因为大多数这样的系统具有在隔行扫描和非隔行扫描操作之间切换的手段,并且由于隔行扫描和非隔行扫描模式具有相对定时变化,所以两个或更多个这样的闭合自由运行系统之间的时序可以同步。 该方法允许与不准确的定时参考同步。 垂直显示定时是自由运行的振荡器,并且使用隔行/非隔行扫描模式转换作为定时调整装置。 数据在连接正在同步的两个系统的通信介质中的实际到达时间与预期到达时间有关,以提供时钟参考。

    Video game enhancer with intergral modem and smart card interface
    4.
    发明授权
    Video game enhancer with intergral modem and smart card interface 失效
    视频游戏增强器,具有内部调制解调器和智能卡接口

    公开(公告)号:US5624316A

    公开(公告)日:1997-04-29

    申请号:US254154

    申请日:1994-06-06

    CPC classification number: A63F13/48 A63F13/02 A63F13/12 A63F13/95

    Abstract: A video game enhancement system for modifying and enhancing the operation of a video game is disclosed. The system includes: 1) a processor interface for coupling the video game enhancement system with a processor; 2) a memory interface for coupling the video game enhancement system with a first memory having executable game logic residing therein; 3) a second memory having executable enhancement logic residing therein; and 4) control logic including: a) logic for detecting an access to a patch address by the processor; b) logic for directing the processor to access an exception region in the second memory upon detection of the access to the patch address, the access to the exception region causing activation of an exception mode; and c) redirection logic for redirecting memory accesses by the processor from the first memory to the second memory for a plurality of memory accesses upon activation of the exception mode, the processor thereby executing a portion of the executable enhancement logic. The the control logic of the video game enhancement system also includes: 5) logic for detecting an access to a transition address by the processor; 6) logic for directing the processor to terminate the exception mode upon detection of the access to the transition address; and 7) the redirection logic further includes logic for redirecting memory accesses by the processor from the second memory to the first memory upon termination of the exception mode, the processor thereby continuing execution of the executable game logic.

    Abstract translation: 公开了一种用于修改和增强视频游戏的操作的视频游戏增强系统。 该系统包括:1)用于将视频游戏增强系统与处理器耦合的处理器接口; 2)用于将视频游戏增强系统与驻留在其中的可执行游戏逻辑的第一存储器耦合的存储器接口; 3)具有驻留在其中的可执行增强逻辑的第二存储器; 以及4)控制逻辑,包括:a)用于检测所述处理器对所述补丁地址的访问的逻辑; b)用于在检测到对所述补丁地址的访问时引导所述处理器访问所述第二存储器中的异常区域的逻辑,所述异常区域的访问引起异常模式的激活; 以及c)重定向逻辑,用于在激活所述异常模式时将所述处理器的存储器访问重定向到所述第二存储器以用于多个存储器访问,所述处理器由此执行所述可执行增强逻辑的一部分。 视频游戏增强系统的控制逻辑还包括:5)用于检测处理器对转换地址的访问的逻辑; 6)用于在检测到对转换地址的访问时指示处理器终止异常模式的逻辑; 以及7)重定向逻辑还包括用于在异常模式终止时将处理器的存储器访问重定向到第一存储器的逻辑,因此处理器继续执行可执行游戏逻辑。

    System and methods for planned evolution and obsolescence of multiuser spectrum

    公开(公告)号:US10425134B2

    公开(公告)日:2019-09-24

    申请号:US13233006

    申请日:2011-09-14

    Abstract: A system and method are described which enable planned evolution and obsolescence of multiuser wireless spectrum. One embodiment of such a system includes one or multiple centralized processors and one or multiple distributed nodes that communicate via wireline or wireless connections. The distributed nodes may share their identification number and other reconfigurable system parameters with the centralized processor. The information about all distributed nodes may be stored in a database that is shared by all centralized processors. The reconfigurable system parameters may comprise power emission, frequency band, modulation/coding scheme. The distributed nodes may be software defined radios such as FPGA, DSP, GPU and/or GPCPU that run algorithms for baseband signal processing and may be reconfigured remotely by the centralized processor. A cloud wireless system may be used wherein the distributed nodes are reconfigured periodically or instantly to adjust to the evolving wireless architecture.

    Interference management, handoff, power control and link adaptation in distributed-input distributed-output (DIDO) communication systems

    公开(公告)号:US10200094B2

    公开(公告)日:2019-02-05

    申请号:US12802988

    申请日:2010-06-16

    Abstract: A system and method are described herein employing a plurality of distributed transmitting antennas to create locations in space with zero RF energy. In one embodiment, when M transmit antennas are employed, it is possible to create up to (M−1) points of zero RF energy in predefined locations. In one embodiment of the invention, the points of zero RF energy are wireless devices and the transmit antennas are aware of the channel state information (CSI) between the transmitters and the receivers. In one embodiment, the CSI is computed at the receivers and fed back to the transmitters. In another embodiment, the CSI is computed at the transmitter via training from the receivers, assuming channel reciprocity is exploited. The transmitters may utilize the CSI to determine the interfering signals to be simultaneously transmitted. In one embodiment, block diagonalization (BD) precoding is employed at the transmit antennas to generate points of zero RF energy.

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