公开(公告)号：US07785982B2

公开(公告)日：2010-08-31

申请号：US11620224

申请日：2007-01-05

申请人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L21/76

CPC分类号： H01L21/823807 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02628 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/78

摘要： Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

摘要翻译： 提供了在诸如Si，Ge，SiGe和GaAs的各种半导体衬底上电沉积锗的方法。 电沉积锗可以形成为覆盖或图案化的膜，并且可以通过后续退火使固相外延结晶到下面的半导体衬底的取向。 这些电镀锗层可以用作互补金属氧化物半导体（CMOS）电路中的高迁移率沟道场效应晶体管（FET）的沟道区。

公开(公告)号：US20080164493A1

公开(公告)日：2008-07-10

申请号：US11620224

申请日：2007-01-05

申请人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L29/778 ,  H01L21/208

CPC分类号： H01L21/823807 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02628 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/78

摘要： Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

摘要翻译： 提供了在诸如Si，Ge，SiGe和GaAs的各种半导体衬底上电沉积锗的方法。 电沉积锗可以形成为覆盖或图案化的膜，并且可以通过后续退火使固相外延结晶到下面的半导体衬底的取向。 这些电镀锗层可以用作互补金属氧化物半导体（CMOS）电路中的高迁移率沟道场效应晶体管（FET）的沟道区。

公开(公告)号：US08823143B2

公开(公告)日：2014-09-02

申请号：US12541499

申请日：2009-08-14

申请人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L21/02

CPC分类号： H01L21/823807 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02628 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/78

摘要： Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

摘要翻译： 提供了在诸如Si，Ge，SiGe和GaAs的各种半导体衬底上电沉积锗的方法。 电沉积锗可以形成为覆盖或图案化的膜，并且可以通过后续退火使固相外延结晶到下面的半导体衬底的取向。 这些电镀锗层可以用作互补金属氧化物半导体（CMOS）电路中的高迁移率沟道场效应晶体管（FET）的沟道区。

公开(公告)号：US20090302353A1

公开(公告)日：2009-12-10

申请号：US12541499

申请日：2009-08-14

申请人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L29/165 ,  H01L29/16 ,  H01L29/78 ,  H01L27/092 ,  H01L29/12

CPC分类号： H01L21/823807 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02628 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/78

摘要： Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

摘要翻译： 提供了在诸如Si，Ge，SiGe和GaAs的各种半导体衬底上电沉积锗的方法。 电沉积锗可以形成为覆盖或图案化的膜，并且可以通过后续退火使固相外延结晶到下面的半导体衬底的取向。 这些电镀锗层可以用作互补金属氧化物半导体（CMOS）电路中的高迁移率沟道场效应晶体管（FET）的沟道区。

公开(公告)号：US20130126493A1

公开(公告)日：2013-05-23

申请号：US13302427

申请日：2011-11-22

申请人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Keith E. Fogel ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Norma E. Sosa Cortes ,  Ning Li ,  Ibrahim Alhomoudi

发明人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Keith E. Fogel ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Norma E. Sosa Cortes ,  Ning Li ,  Ibrahim Alhomoudi

IPC分类号： B23K26/00

CPC分类号： H01L21/268 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/50 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/6835 ,  H01L2221/68327

摘要： Laser ablation can be used to form a trench within at least a blanket layer of a stressor layer that is atop a base substrate. A non-ablated portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can also be used to form a trench within a blanket material stack including at least a plating seed layer. A stressor layer is formed on the non-ablated portions of the material stack and one portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can be further used to form a trench that extends through a blanket stressor layer and into the base substrate itself. The trench has an edge that defines the edge of the material layer region to be spalled.

公开(公告)号：US20120309269A1

公开(公告)日：2012-12-06

申请号：US13150813

申请日：2011-06-01

申请人： Maha M. Khayyat ,  Norma E. Sosa Cortes ,  Katherine L. Saenger ,  Stephen W. Bedell ,  Devendra K. Sadana

发明人： Maha M. Khayyat ,  Norma E. Sosa Cortes ,  Katherine L. Saenger ,  Stephen W. Bedell ,  Devendra K. Sadana

IPC分类号： B24B1/00

CPC分类号： H01L21/187

摘要： Method to (i) introduce additional control into a material spalling process, thus improving both the crack initiation and propagation, and (ii) increase the range of selectable spalling depths are provided. In one embodiment, the method includes providing a stressor layer on a surface of a base substrate at a first temperature which is room temperature. Next, the base substrate including the stressor layer is brought to a second temperature which is less than room temperature. The base substrate is spalled at the second temperature to form a spalled material layer. Thereafter, the spalled material layer is returned to room temperature, i.e., the first temperature.

摘要翻译： 方法：（i）对材料剥落过程引入额外的控制，从而改善裂纹的产生和传播，并提供（ii）提高选择性剥落深度的范围。 在一个实施例中，该方法包括在室温下的第一温度下在基底基板的表面上提供应力层。 接下来，包括应力层的基底衬底达到小于室温的第二温度。 基底基板在第二温度下剥离以形成剥离的材料层。 此后，剥离的材料层返回到室温，即第一温度。

公开(公告)号：US20120118383A1

公开(公告)日：2012-05-17

申请号：US12946216

申请日：2010-11-15

申请人： Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Wilfried E. Haensch ,  Steven J. Koester ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Wilfried E. Haensch ,  Steven J. Koester ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/0264 ,  H01L31/18

CPC分类号： H01L27/142 ,  H01L31/02008 ,  H01L31/0747 ,  H01L31/075 ,  H01L31/076 ,  H01L31/078 ,  H01L31/1804 ,  H01L31/202 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer.

摘要翻译： 自主集成电路（IC）包括形成在作为处理衬底的绝缘体上硅（SOI）衬底的底部衬底上的太阳能电池; 位于太阳能电池顶部的SOI衬底的绝缘层; 以及形成在位于绝缘层顶部的SOI衬底的顶部半导体层上的器件层，其中器件层的顶部接触电连接到太阳能电池的底部接触，使得太阳能电池能够通电 设备层。

公开(公告)号：US20080258220A1

公开(公告)日：2008-10-23

申请号：US12128040

申请日：2008-05-28

申请人： Stephen W. Bedell ,  Joel P. De Souza ,  Zhibin Ren ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi

发明人： Stephen W. Bedell ,  Joel P. De Souza ,  Zhibin Ren ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi

IPC分类号： H01L27/12 ,  H01L21/8234

CPC分类号： H01L29/66628 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

摘要翻译： 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源极/漏极（S / D）区域的潜在问题）的方法， 以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

公开(公告)号：US08933456B2

公开(公告)日：2015-01-13

申请号：US13616322

申请日：2012-09-14

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L29/38 ,  H01L21/02 ,  H01L21/762

CPC分类号： H01L21/0262 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/76254

摘要： A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed.

摘要翻译： 含锗层沉积在单一晶体体硅衬底上，包括足以以原子浓度掺入1％-50％的氧的氧分压水平。 含锗层的厚度优选被限制以保持与底层硅衬底的一定程度的外延对准。 任选地，可以在含锗层上生长或替代含锗层。 随后将至少部分结晶的硅层沉积在含锗层上。 手柄基板结合到至少部分结晶的硅层。 本体硅衬底，含锗层，至少部分结晶的硅层和处理衬底的组件在含锗层内被切割以提供复合衬底，该复合衬底包括处理衬底和至少部分结晶的硅 层。 去除复合衬底上任何剩余的含锗层。

公开(公告)号：US08916450B2

公开(公告)日：2014-12-23

申请号：US13565378

申请日：2012-08-02

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ibrahim Alhomoudi

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ibrahim Alhomoudi

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/00

CPC分类号： H01L21/304 ,  B26F3/00 ,  C30B33/00 ,  C30B33/06 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/321 ,  H01L31/1892 ,  Y02E10/50 ,  Y10T225/10

摘要： Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.

摘要翻译： 利用剥落的材料层从基底基板上去除材料层的方法，其中在剥离期间模式III应力即垂直于在基底基板中产生的断裂面的应力减小。 在剥落过程中模式III应力的显着降低导致剥落过程，其中剥离材料在其一个边缘处具有较小的表面粗糙度，与现有技术的剥离过程相比，其中存在模式III应力并与剥落相竞争。