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    Method of improving the quality of defective semiconductor material
    1.
    发明授权
    Method of improving the quality of defective semiconductor material 失效
    提高缺陷半导体材料质量的方法

    公开(公告)号：US06825102B1

    公开(公告)日：2004-11-30

    申请号：US10664714

    申请日：2003-09-18

    申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Shreesh Narasimha ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Shreesh Narasimha ,  Devendra K. Sadana

    IPC分类号： H01L21263

    CPC分类号： H01L21/02667 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/2022 ,  Y10S438/933

    摘要： A method in which a defective semiconductor crystal material is subjected to an amorphization step followed by a thermal treatment step is provided. The amorphization step amorphizes, partially or completely, a region, including the surface region, of a defective semiconductor crystal material. A thermal treatment step is next performed so as to recrystallize the amorphized region of the defective semiconductor crystal material. The recrystallization is achieved in the present invention by solid-phase crystal regrowth from the non-amorphized region of the defective semiconductor crystal material.

    摘要翻译： 提供一种方法，其中对缺陷半导体晶体材料进行非晶化步骤之后进行热处理步骤。 非晶化步骤使部分地或完全地形成缺陷半导体晶体材料的区域，包括表面区域。 接下来进行热处理步骤，以便使缺陷半导体晶体材料的非晶化区域再结晶。 通过从缺陷半导体晶体材料的非非晶化区域的固相晶体再生长，在本发明中实现了重结晶。

    Multiple crystallographic orientation semiconductor structures
    2.
    发明授权
    Multiple crystallographic orientation semiconductor structures 有权
    多晶体取向半导体结构

    公开(公告)号：US07993990B2

    公开(公告)日：2011-08-09

    申请号：US12757567

    申请日：2010-04-09

    申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

    发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

    摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

    摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

    MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES
    3.
    发明申请
    MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES 有权
    多晶体取向半导体结构

    公开(公告)号：US20100197118A1

    公开(公告)日：2010-08-05

    申请号：US12757567

    申请日：2010-04-09

    申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

    发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

    IPC分类号： H01L21/20

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

    摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

    摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

    Bulk substrate FET integrated on CMOS SOI
    7.
    发明授权
    Bulk substrate FET integrated on CMOS SOI 有权
    集成在CMOS SOI上的散装衬底FET

    公开(公告)号：US08232599B2

    公开(公告)日：2012-07-31

    申请号：US12683456

    申请日：2010-01-07

    申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    IPC分类号： H01L27/12 ,  H01L21/86

    CPC分类号： H01L27/1207 ,  H01L21/84

    摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

    摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

    BULK SUBSTRATE FET INTEGRATED ON CMOS SOI
    8.
    发明申请
    BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
    集成在CMOS SOI上的基极FET

    公开(公告)号：US20120187492A1

    公开(公告)日：2012-07-26

    申请号：US13425681

    申请日：2012-03-21

    申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    IPC分类号： H01L27/088

    CPC分类号： H01L27/1207 ,  H01L21/84

    摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

    摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

    METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE
    9.
    发明申请
    METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE 有权
    使用低温退火工艺制造器件的方法，器件和设计结构

    公开(公告)号：US20120180010A1

    公开(公告)日：2012-07-12

    申请号：US13421400

    申请日：2012-03-15

    申请人： Anthony G. DOMENICUCCI ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

    发明人： Anthony G. DOMENICUCCI ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

    IPC分类号： G06F17/50

    CPC分类号： H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7847

    摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

    摘要翻译： 提供了使用退火处理序列制造器件的方法。 更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。 该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。 该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。

    COMPACT MODEL METHODOLOGY FOR PC LANDING PAD LITHOGRAPHIC ROUNDING IMPACT ON DEVICE PERFORMANCE
    10.
    发明申请
    COMPACT MODEL METHODOLOGY FOR PC LANDING PAD LITHOGRAPHIC ROUNDING IMPACT ON DEVICE PERFORMANCE 有权
    用于PC路面平台的简化模型方法对设备性能的影响

    公开(公告)号：US20110225562A1

    公开(公告)日：2011-09-15

    申请号：US13100584

    申请日：2011-05-04

    申请人： Dureseti Chidambarrao ,  Gerald M. Davidson ,  Paul A. Hyde ,  Judith H. McCullen ,  Shreesh Narasimha

    发明人： Dureseti Chidambarrao ,  Gerald M. Davidson ,  Paul A. Hyde ,  Judith H. McCullen ,  Shreesh Narasimha

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5036

    摘要： A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance. Then, transistor model parameter values in a transistor compact model are updated for the transistor device to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a device simulation may then include the deltaW adder values to quantify the influence of the lithographic rounding effect of the landing pad feature.

    摘要翻译： 一种用于对具有有源器件区域，栅极结构并且包括连接到栅极结构并且设置在有源器件区域上方的导线特征来建模半导体晶体管器件结构的方法和计算机程序产品，所述导电线特征包括导电层 衬垫特征设置在待建模的电路中的有源器件区域的边缘附近。 该方法包括确定由着陆焊盘特征限定的边缘与有源器件区域的边缘之间的距离，以及通过建模着陆焊盘特征的光刻圆整效应，确定作为功能的有源器件区域的宽度变化 由着陆垫特征限定的边缘到活动设备区域的边缘之间的距离。 根据这些数据，有源器件区域宽度（deltaW加法器）的有效变化与确定的距离有关。 然后，晶体管紧凑型模型中的晶体管模型参数值被更新为晶体管器件，以包括要添加到内置deltaW值的ΔW加法器值。 在设备仿真中使用的网表可以包括deltaW加法器值，以量化着陆垫特征的光刻舍入效应的影响。