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59 条记录 (耗时 0.027 秒)

    Integrated device having MOS transistors which enable positive and negative voltage swings
    2.
    发明授权
    Integrated device having MOS transistors which enable positive and negative voltage swings 失效
    具有MOS晶体管的集成器件，其实现正负电压摆幅

    公开(公告)号：US5321293A

    公开(公告)日：1994-06-14

    申请号：US88945

    申请日：1993-07-12

    申请人： Mohamad M. Mojaradi ,  Tuan Vo ,  Jaime Lerma ,  Steven A. Buhler

    发明人： Mohamad M. Mojaradi ,  Tuan Vo ,  Jaime Lerma ,  Steven A. Buhler

    IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L27/092 ,  H03K17/30 ,  H03K3/01

    CPC分类号： H01L27/0925 ,  H01L27/0251 ,  H03K17/302

    摘要： A semiconductor circuit integrated with CMOS circuits for receiving a TTL input voltage and generating a large negative and positive voltage swing with respect to p-type or n-type substrate is disclosed. This invention is based on elimination of the electro-static discharge (ESD) protection circuit which is a requirement for any integrated circuit. Eliminating the ESD protection circuit also eliminates the clamping feature of the ESD protection circuit and therefore the circuit can be driven to negative voltages for PMOS circuits and to positive voltages for NMOS circuits. This provides the possibility of connecting the drain of a a P-channel type metal oxide silicon field effect (PMOS) transistor, which is fabricated on a p-type substrate within an n-well, to a voltage below the the substrate voltage. Also, in a n-channel type metal oxide silicon field effect (NMOS) transistor which is fabricated on a n-type substrate within a P-well, the drain can be connected to voltages higher than the substrate voltage. Utilizing this feature of a MOS transistor provides a way to design an integrated circuit which can handle negative voltage swings as well as positive voltage swings.

    摘要翻译： 公开了一种与用于接收TTL输入电压并且相对于p型或n型衬底产生大的负和正电压摆幅的CMOS电路集成的半导体电路。 本发明基于消除作为任何集成电路的要求的静电放电（ESD）保护电路。 消除ESD保护电路也消除了ESD保护电路的钳位特性，因此电路可以被驱动到PMOS电路的负电压和NMOS电路的正电压。 这提供了将制造在n阱内的p型衬底上的P沟道型金属氧化物硅场效应（PMOS）晶体管的漏极连接到低于衬底电压的电压的可能性。 此外，在P阱内的n型衬底上制造的n沟道型金属氧化物硅场效应（NMOS）晶体管中，漏极可以连接到高于衬底电压的电压。 利用MOS晶体管的这一特征提供了一种设计可以处理负电压摆幅以及正电压摆幅的集成电路的方法。

    High voltage integrated circuit diode with a charge injecting node
    3.
    发明授权
    High voltage integrated circuit diode with a charge injecting node 失效
    具有电荷注入节点的高压集成电路二极管

    公开(公告)号：US5757065A

    公开(公告)日：1998-05-26

    申请号：US726456

    申请日：1996-10-04

    申请人： Steven A. Buhler ,  Jaime Lerma

    发明人： Steven A. Buhler ,  Jaime Lerma

    IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/861 ,  H01L29/868 ,  H01L29/06 ,  H01L31/0352

    CPC分类号： H01L29/868 ,  H01L27/0629

    摘要： An integrated CMOS diode with an injection ring which enables construction of an integrated CMOS diode that has the performance characteristics of a high impedance value, when the diode is in the off state, and low impedance, when the diode is in the on state in addition to high breakdown voltages using standard CMOS processing techniques to construct the integrated circuit diode.

    摘要翻译： 具有注入环的集成CMOS二极管，当二极管处于截止状态时，能够构建具有高阻抗值的性能特性的集成CMOS二极管，并且当二极管处于导通状态时，其具有低阻抗 使用标准CMOS处理技术来构建集成电路二极管的高击穿电压。

    Multi-layer monolithic fluid ejectors using piezoelectric actuation
    6.
    发明授权
    Multi-layer monolithic fluid ejectors using piezoelectric actuation 有权
    使用压电驱动的多层单片液体喷射器

    公开(公告)号：US07905580B2

    公开(公告)日：2011-03-15

    申请号：US12273575

    申请日：2008-11-19

    申请人： Baomin Xu ,  Steven A. Buhler ,  Stephen D. White ,  Scott Jong Ho Limb

    发明人： Baomin Xu ,  Steven A. Buhler ,  Stephen D. White ,  Scott Jong Ho Limb

    IPC分类号： B41J2/045

    CPC分类号： B41J2/14233 ,  B41J2/161 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1634 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1643 ,  B41J2/1646 ,  B41J2002/14475 ,  Y10T29/42 ,  Y10T29/49401

    摘要： A fluid ejector including a silicon wafer having a first side and a second side. A multi-layer monolithic structure is formed on the first side of the silicon wafer. The multi-layer monolithic structure includes a first structure layer formed on the first side of the silicon wafer, and the first structure layer has an aperture. A second structure layer has a horizontal portion and closed, filled trenches or vertical sidewalls. The first structure layer, horizontal portion and the closed, filled trenches or vertical sidewalls of the second structure layer define a fluid cavity. An actuator is associated with the horizontal portion of the second structure layer, and an etched portion of the silicon wafer defines an open area which exposes the aperture in the first structure layer.

    摘要翻译： 一种流体喷射器，包括具有第一侧和第二侧的硅晶片。 在硅晶片的第一侧上形成多层整体结构。 多层单片结构包括形成在硅晶片的第一侧上的第一结构层，第一结构层具有孔。 第二结构层具有水平部分和闭合的填充沟槽或垂直侧壁。 第二结构层的第一结构层，水平部分和闭合填充的沟槽或垂直侧壁限定流体腔。 致动器与第二结构层的水平部分相关联，并且硅晶片的蚀刻部分限定露出第一结构层中的孔的开放区域。

    Scan non-linearity correction using frequency modulation and synchronization with a master clock
    9.
    发明授权
    Scan non-linearity correction using frequency modulation and synchronization with a master clock 有权
    使用频率调制和主时钟同步扫描非线性校正

    公开(公告)号：US07193643B2

    公开(公告)日：2007-03-20

    申请号：US10284543

    申请日：2002-10-30

    申请人： Mehrdad Zomorrodi ,  Steven A. Buhler

    发明人： Mehrdad Zomorrodi ,  Steven A. Buhler

    IPC分类号： B41J2/435

    CPC分类号： H04N1/053 ,  H04N1/1135 ,  H04N1/12 ,  H04N2201/02439 ,  H04N2201/04772 ,  H04N2201/04793 ,  H04N2201/04794

    摘要： An electronic circuit is utilized to correct scan non-linearity of a raster output scanner. The circuit modulates a clock frequency to match a scan linearity error profile. Because it is a separate circuit, the exiting closed-loop clock generator does not need to be modified. The correction circuit synchronizes itself with the clock signal using a counter/subtractor phase detector, which ensures that the phase and frequency of the internal clock matches the phase and frequency of the master.

    摘要翻译： 使用电子电路来校正光栅输出扫描器的扫描非线性。 电路调制时钟频率以匹配扫描线性误差轮廓。 因为它是一个单独的电路，所以不需要修改出来的闭环时钟发生器。 校正电路使用计数器/减法器相位检测器与时钟信号同步，确保内部时钟的相位和频率与主器件的相位和频率匹配。

    Process insensitive electronic driver circuitry for integrated RF switching diodes
    10.
    发明授权
    Process insensitive electronic driver circuitry for integrated RF switching diodes 失效
    用于集成射频开关二极管的过程不敏感的电子驱动器电路

    公开(公告)号：US06650151B2

    公开(公告)日：2003-11-18

    申请号：US10025476

    申请日：2001-12-26

    申请人： Mostafa R. Yazdy ,  Lamar T. Baker ,  Steven A. Buhler

    发明人： Mostafa R. Yazdy ,  Lamar T. Baker ,  Steven A. Buhler

    IPC分类号： H03B100

    CPC分类号： H01L29/8611 ,  B41J2/14008 ,  H01L29/0692

    摘要： An electronic driver circuitry for an RF switch diode used in Acoustic Ink Jet Printing (AIP) systems is disclosed The electronic driver circuitry consists of a PMOS transistor and a poly resistor used to control the on/off states of the RF switch diode wherein the drive current for the RF switch diode is the same as the current in the PMOS transistor. To compensate for undesirable variations in the RF switch diode, the driver circuitry is designed such that the current in the PMOS transistor is adjusted in an opposite direction to cancel the unwanted variations.

    摘要翻译： 公开了一种用于声喷墨打印（AIP）系统中用于RF开关二极管的电子驱动器电路。电子驱动器电路由用于控制RF开关二极管的导通/截止状态的PMOS晶体管和多晶硅电阻组成，其中驱动 RF开关二极管的电流与PMOS晶体管中的电流相同。 为了补偿RF开关二极管中的不期望的变化，驱动器电路被设计成使得PMOS晶体管中的电流在相反方向上被调整以消除不期望的变化。