-
公开(公告)号：US5531326A
公开(公告)日：1996-07-02
申请号：US367816
申请日：1995-01-03
IPC分类号： B65D5/00 , B65D6/36 , B65D21/02 , B65D21/032
CPC分类号： B65D21/0215 , B65D5/006
摘要： A container reinforcement that comprises a pair of interlockable members, at least one of which is movable with respect to the other. The interlockable members have cooperable lock portions that interfit with one another and can be used to manually, removably attach the reinforcement to a container. A container using such a reinforcement.
摘要翻译： 一种容器加强件，其包括一对可互锁构件，其中至少一个可相对于另一构件移动。 可互锁构件具有彼此相互配合的可配合的锁定部分，并且可以用于手动地，可移除地将加强件附接到容器。 使用这种钢筋的容器。
-
公开(公告)号：US08468931B2
公开(公告)日：2013-06-25
申请号：US12725802
申请日：2010-03-17
申请人： James B. Johnson
发明人： James B. Johnson
摘要： A fluid motor and a control system that includes an electronic controller and a mechanical servo to position a fluid motor. The electronic controller is combined with a non-electronic self storing position feedback device. The electronic controller is capable of providing accurate positioning and the positioning is maintained with a mechanical servo mechanism. The fluid motor can be either hydraulically or pneumatically operated.
摘要翻译： 一种流体马达和控制系统，其包括电子控制器和用于定位流体马达的机械伺服。 电子控制器与非电子自存位置反馈装置组合。 电子控制器能够提供精确的定位，并且利用机械伺服机构来保持定位。 流体马达可以是液压或气动操作。
-
3.发明授权Memory system and method using stacked memory device dice, and system using the memory system 有权内存系统和方法采用堆叠式存储设备骰子，系统采用内存系统公开(公告)号：US07855931B2
公开(公告)日：2010-12-21
申请号：US12176951
申请日：2008-07-21
IPC分类号： G11C8/00
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
摘要翻译： 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整应用于每个存储器件管芯的相应选通信号（例如读选通信号）的定时来控制读数据或其他信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。
-
4.发明授权公开(公告)号：US07813192B2
公开(公告)日：2010-10-12
申请号：US12489270
申请日：2009-06-22
申请人： Joo S. Choi , James B. Johnson
发明人： Joo S. Choi , James B. Johnson
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4096 , G11C2207/107
摘要： A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal.
摘要翻译： 信号捕获系统和方法用于使用具有选通信号转换的前导码的数据选通信号捕获数据信号。 该系统包括接收数据信号的数据锁存电路。 数据锁存电路由数据选通信号的转换来计时，以捕获对应于数据信号的各个数据位。 解码器接收存储器命令信号，并且如果命令信号对应于读取或写入命令，则在接收到存储器命令信号的延迟周期之后产生数据起始信号。 读/写命令信号的接收由控制电路用于识别有效读或写数据信号的开始。 然后，控制电路响应于数据开始信号输出捕获的数据信号，从而忽略数据选通信号的前同步码中的转换。
-
5.发明申请MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM 有权使用堆叠存储器设备的存储器系统和方法，以及使用存储器系统的系统公开(公告)号：US20100014364A1
公开(公告)日：2010-01-21
申请号：US12176951
申请日：2008-07-21
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
摘要翻译： 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整施加到每个存储器件管芯的各个选通信号（例如读取选通信号）的定时来控制读取数据或其他信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。
-
公开(公告)号：US07028208B2
公开(公告)日：2006-04-11
申请号：US11018810
申请日：2004-12-21
申请人： James B. Johnson , Feng D. Lin
发明人： James B. Johnson , Feng D. Lin
CPC分类号： G11C7/22 , G06F1/12 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/107
摘要： A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.
-
公开(公告)号：US6167196A
公开(公告)日：2000-12-26
申请号：US5320
申请日：1998-01-09
申请人： Charles A. Huggins, Jr. , Kostas Kaplanis , Barry W. Smith , Larry L. McGrain , James B. Johnson , Thomas H. Mills
发明人： Charles A. Huggins, Jr. , Kostas Kaplanis , Barry W. Smith , Larry L. McGrain , James B. Johnson , Thomas H. Mills
CPC分类号： H05B3/44
摘要： A portable electric space heater having a power cord with a male electrical plug and having easily replaceable quartz heating elements so that an unskilled person can remove and replace a heating element with a minimum of time, tools and skill. The heating elements are removably mounted by sockets within the heater housing behind a grill. One edge of the grill is pivotally connected to the housing and an opposite edge is connected to the housing by a latch member formed on the grill. Access to the heating elements can be obtained by unlatching the grill using the male plug as a tool.
摘要翻译： 一种便携式电动空间加热器，其具有带有公电插头的电源线，并且具有易于更换的石英加热元件，使得不熟练的人能够以最少的时间，工具和技术来移除和更换加热元件。 加热元件由加热器壳体内的插座可拆卸地安装在格栅后面。 格栅的一个边缘可枢转地连接到壳体，并且相对边缘通过形成在格栅上的闩锁构件连接到壳体。 可以通过使用公插头作为工具将格栅解锁来获得对加热元件的访问。
-
公开(公告)号：US5705546A
公开(公告)日：1998-01-06
申请号：US662572
申请日：1996-06-13
申请人： Sivaram Krishnan , James B. Johnson
发明人： Sivaram Krishnan , James B. Johnson
IPC分类号： C08K5/1515 , C08L69/00 , C08K5/15
CPC分类号： C08K5/1515 , C08L69/00
摘要： A thermoplastic molding composition having improved release properties is disclosed. The composition contains a polycarbonate and an additive amount of an epoxy conforming structurally to ##STR1## where R is a member selected from the group consisting of glyceryl and trimethyl propyl radicals, x is 0 to 20 and R' is a C.sub.1-4 alkyl radical.
摘要翻译： 公开了具有改进的脱模性能的热塑性模塑组合物。 组合物含有聚碳酸酯和结构上符合
的环氧树脂的添加量，其中R是选自甘油基和三甲基丙基的成员，x是0至20，R'是C 1-4烷基 。 -
公开(公告)号：US5033280A
公开(公告)日：1991-07-23
申请号：US449105
申请日：1989-12-07
申请人： James B. Johnson
发明人： James B. Johnson
CPC分类号： E05B13/001 , E05B67/36 , F16B41/007 , F16L35/00 , Y10T70/5628 , Y10T70/5867 , Y10T70/8649
摘要： A security lock for detachably securing a hose fitting includes two hinged members connected by a lock. The hinge members surround the hose fitting. The lock is compact to fit in small areas. The lock is used for securing watering systems on recreational vehicles.
摘要翻译： 用于可拆卸地固定软管接头的安全锁包括通过锁连接的两个铰链构件。 铰链部件围绕软管接头。 锁紧凑，适合小区域。 该锁用于确保休闲车辆上的浇水系统。
-
10.发明授权公开(公告)号：US07206956B2
公开(公告)日：2007-04-17
申请号：US11351277
申请日：2006-02-08
申请人： James B. Johnson , Feng D. Lin
发明人： James B. Johnson , Feng D. Lin
CPC分类号： G11C7/22 , G06F1/12 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/107
摘要： A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.
摘要翻译： 提供了用于补偿由同步动态随机存取存储器件（SDRAM）产生的输出数据信号中的占空比失真的技术。 SDRAM的输出锁存器由延迟锁定环（DLL）产生的输出时钟信号驱动。 输出时钟信号相对于由DLL接收的参考时钟信号相移，使得从输出锁存器移除的数据与参考时钟信号同步。 此外，输出时钟信号的占空比以与由输出锁存器引入的占空比失真相反的关系被调整。 结果，输出数据信号具有减小的占空比失真。
-
-
-
-
-
-
-
-
-
搜索结果
42 条记录 (耗时 0.031 秒)
