公开(公告)号：US20120106281A1

公开(公告)日：2012-05-03

申请号：US13282830

申请日：2011-10-27

申请人： Sua KIM ,  Chul-woo PARK ,  Hong-sun HWANG ,  Hak-soo YU

发明人： Sua KIM ,  Chul-woo PARK ,  Hong-sun HWANG ,  Hak-soo YU

IPC分类号： G11C7/06 ,  G11C8/08 ,  G11C8/10 ,  G11C7/12

CPC分类号： G11C7/18 ,  G11C7/06 ,  G11C2207/002 ,  G11C2207/005

摘要： A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal.

摘要翻译： 半导体存储器件包括至少一个存储单元块和至少一个连接单元。 所述至少一个存储单元块具有包括连接到第一位线的至少一个第一存储单元的第一区域和包括连接到第二位线的至少一个第二存储器单元的第二区域。 所述至少一个连接单元被配置为基于第一控制信号选择性地将第一位线连接到对应的位线读出放大器，并且被配置为经由对应的全局位选择性地将第二位线连接到对应的位线读出放大器 基于第二控制信号。

公开(公告)号：US20120063194A1

公开(公告)日：2012-03-15

申请号：US13224410

申请日：2011-09-02

申请人： In-gyu BAEK ,  Hong-sun HWANG ,  Hak-soo YU ,  Chul-woo PARK

发明人： In-gyu BAEK ,  Hong-sun HWANG ,  Hak-soo YU ,  Chul-woo PARK

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

摘要： Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

摘要翻译： 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

公开(公告)号：US20130058145A1

公开(公告)日：2013-03-07

申请号：US13604308

申请日：2012-09-05

申请人： Hak-soo YU ,  Uk-song KANG ,  Chul-woo PARK ,  Joo-sun CHOI ,  Hong-Sun HWANG

发明人： Hak-soo YU ,  Uk-song KANG ,  Chul-woo PARK ,  Joo-sun CHOI ,  Hong-Sun HWANG

IPC分类号： G11C29/00 ,  G11C15/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/783 ,  G11C2029/0409 ,  G11C2029/4402

摘要： A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.

摘要翻译： 半导体器件包括包括多个存储单元的第一存储区域; 测试单元，被配置为测试所述第一存储器区域，并且从所述多个存储器单元中检测弱位; 以及第二存储器区域，被配置为存储所述第一存储器区域的弱位地址（WBA）以及要存储在所述弱位中的数据，其中所述第一存储器区域和所述第二存储器区域包括不同类型的存储器单元。

公开(公告)号：US20130039135A1

公开(公告)日：2013-02-14

申请号：US13569636

申请日：2012-08-08

申请人： Uk-song KANG ,  Chul-woo PARK ,  Hak-soo YU ,  Hong-sun HWANG

发明人： Uk-song KANG ,  Chul-woo PARK ,  Hak-soo YU ,  Hong-sun HWANG

IPC分类号： G11C7/22

CPC分类号： G11C11/4076 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/4093

摘要： A method of performing write operations in a memory device including a plurality of banks is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.

摘要翻译： 执行在包括多个存储体的存储器件中执行写入操作的方法。 每个银行包括至少包括第一子银行和第二子银行的两个或多个子行。 该方法包括：执行第一行周期以写入第一子行的第一字线，第一行周期包括多个第一子周期，用于执行特定动作的每个子周期; 以及执行第二行周期以写入所述第二子行的第一字线，所述第二行周期包括与所述多个第一子周期相同类型的多个第二子周期。 第一行周期与第二行周期重叠，第一子周期的第一类型子周期与第二子周期的第二类型子周期重叠，第一类型和第二类型是不同类型。

公开(公告)号：US20120099389A1

公开(公告)日：2012-04-26

申请号：US13236972

申请日：2011-09-20

申请人： Chul-woo PARK ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

发明人： Chul-woo PARK ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

IPC分类号： G11C11/402 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808 ,  G06F2213/0038 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/40626 ,  G11C2211/4062

摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.

摘要翻译： 存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作 命令。

公开(公告)号：US20160147460A1

公开(公告)日：2016-05-26

申请号：US14852774

申请日：2015-09-14

申请人： Young-soo SOHN ,  Sei-jin KIM ,  Kwang-il PARK ,  Tae-young KIM ,  Chul-woo PARK

发明人： Young-soo SOHN ,  Sei-jin KIM ,  Kwang-il PARK ,  Tae-young KIM ,  Chul-woo PARK

IPC分类号： G06F3/06

CPC分类号： G06F9/3004 ,  G06F9/30032 ,  G06F12/00 ,  G06F15/785

摘要： A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

摘要翻译： 提供执行内部复制操作的存储器件。 存储装置可以与内部复制命令一起接收源地址，目的地地址和页面大小信息，将源地址与目的地地址进行比较，并执行内部复制操作。 内部复制操作可以是内部块复制操作，银行间复制操作或内部银行复制操作。 可以基于页面大小信息来执行关于一页数据，半页数据或四分之一页数据的内部复制操作。 存储器件可以作为标志信号输出指示内部复制操作已经完成的复制完成信号。

公开(公告)号：US20090255082A1

公开(公告)日：2009-10-15

申请号：US12254693

申请日：2008-10-20

申请人： Chul-woo PARK ,  Ji-ho Seo

发明人： Chul-woo PARK ,  Ji-ho Seo

IPC分类号： A47L9/00

CPC分类号： A47L5/34 ,  A47L9/0494

摘要： An upright vacuum cleaner has a cleaner body; a suction port assembly hinged to the cleaner body with a drum brush mounted on a front lower surface thereof; and a height adjusting apparatus set to an active mode or an inactive mode. In the active mode, the height adjusting apparatus raises the rear portion of the suction port assembly from an initial height, with the drum brush spaced from a surface, to bring the drum brush into contact with the surface when the cleaner body tilts from an upright position towards the rear of the suction port assembly. In the inactive mode, the rear portion of the suction port assembly remains at the initial height when the cleaner body tilts from the upright position towards the rear of the suction port assembly.

摘要翻译： 立式吸尘器具有清洁器体; 吸入口组件，其与安装在其前下表面上的滚筒刷铰接到吸尘器本体; 以及设定为活动模式或非活动模式的高度调节装置。 在主动模式中，高度调节装置将吸气口组件的后部从初始高度升高，鼓刷与表面间隔开，以使得当清洁器主体从直立件倾斜时，鼓刷与表面接触 位于吸入口组件的后部。 在非活动模式下，当吸尘器主体从直立位置向吸入口组件的后部倾斜时，吸入口组件的后部保持在初始高度。

公开(公告)号：US20160077940A1

公开(公告)日：2016-03-17

申请号：US14683705

申请日：2015-04-10

申请人： Jong-pil SON ,  Chul-woo PARK ,  Su-a KIM

发明人： Jong-pil SON ,  Chul-woo PARK ,  Su-a KIM

IPC分类号： G06F11/20

CPC分类号： G06F11/2094 ,  G06F11/1048 ,  G06F2201/85 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/4402

摘要： The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

摘要翻译： 存储器件包括存储器阵列，控制逻辑和恢复电路。 存储器阵列具有被配置为存储数据的第一区域，被配置为存储故障小区信息的一部分的第二区域以及被配置为存储恢复信息的第三区域。 故障小区信息识别第一区域中的故障小区，并且恢复信息用于恢复存储在所识别的故障小区中的数据。 控制逻辑被配置为存储故障小区信息，将故障小区信息的一部分传送到存储器阵列的第二区域，并且基于访问请求中的地址信息确定是否执行恢复操作，并且部分 存储在第二区域中的故障小区信息。 访问请求是访问第一个区域的请求。 恢复电路被配置为执行恢复操作。

公开(公告)号：US20130083612A1

公开(公告)日：2013-04-04

申请号：US13601725

申请日：2012-08-31

申请人： Jong-pil SON ,  Chul-woo PARK

发明人： Jong-pil SON ,  Chul-woo PARK

IPC分类号： G11C29/00

CPC分类号： G11C29/808 ,  G11C29/4401 ,  G11C2029/4402

摘要： A memory device includes a repair circuit including a fail bit location information table configured to store row and column addresses of a defective cell in a normal area of a memory cell array. The repair circuit also includes a row address comparison unit configured to compare the row address of the defective cell with a row address of a first access cell received from the outside, and to output a first row match signal when the defective cell's row address matches the row address of the first access cell, and a column address comparison unit configured to compare the column address of the defective cell with a column address of the first access cell received from the outside, and to output a first column address replacement signal if the column address of the defective cell is the same as the column address of the first access cell.

摘要翻译： 存储器件包括修复电路，该修复电路包括故障位位置信息表，其被配置为存储存储单元阵列的正常区域中的有缺陷单元的行和列地址。 修复电路还包括行地址比较单元，其被配置为将缺陷单元的行地址与从外部接收的第一存取单元的行地址进行比较，并且当缺陷单元的行地址匹配时，输出第一行匹配信号 第一接入小区的行地址，以及列地址比较单元，被配置为将缺陷小区的列地址与从外部接收的第一接入小区的列地址进行比较，并且如果列 故障小区的地址与第一接入小区的列地址相同。