公开(公告)号：US08158506B2

公开(公告)日：2012-04-17

申请号：US12115254

申请日：2008-05-05

申请人： Suku Kim ,  James J. Murphy ,  Michael D. Gruenhagen ,  Matthew R. Reynolds ,  Romel N. Manatad ,  Jan Vincent C. Mancelita

发明人： Suku Kim ,  James J. Murphy ,  Michael D. Gruenhagen ,  Matthew R. Reynolds ,  Romel N. Manatad ,  Jan Vincent C. Mancelita

IPC分类号： H01L21/44

CPC分类号： H01L21/74 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.

摘要翻译： 描述了半导体器件中使用的晶片的局部变薄方法和由这些方法形成的结构。 该方法使半导体晶片的背面薄的局部区域形成具有在晶片（或管芯）内重复的双向通道设计的凹槽，使得没有直通道线穿过晶片（或管芯）。 双向图案设计保持通道不与晶片的晶体取向对齐。 然后通过将适当尺寸的焊球落入凹槽中然后通过焊球落下工艺填充凹陷，然后退火晶片以回流焊球并使其平坦化。 回流工艺开始从底部向上填充凹槽，从而避免了空隙形成和回流焊料中形成的空气阱。 还描述了其它实施例。

公开(公告)号：US20120168947A1

公开(公告)日：2012-07-05

申请号：US13404317

申请日：2012-02-24

申请人： Suku Kim ,  James J. Murphy ,  Michael D. Gruenhagen ,  Matthew R. Reynolds ,  Romel N. Manatad ,  Jan Vincent C. Mancelita

发明人： Suku Kim ,  James J. Murphy ,  Michael D. Gruenhagen ,  Matthew R. Reynolds ,  Romel N. Manatad ,  Jan Vincent C. Mancelita

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L21/74 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.

摘要翻译： 描述了半导体器件中使用的晶片的局部变薄方法和由这些方法形成的结构。 该方法使半导体晶片的背面薄的局部区域形成具有在晶片（或管芯）内重复的双向通道设计的凹槽，使得没有直通道线穿过晶片（或管芯）。 双向图案设计保持通道不与晶片的晶体取向对齐。 然后通过将适当尺寸的焊球落入凹槽中然后通过焊球落下工艺填充凹陷，然后退火晶片以回流焊球并使其平坦化。 回流工艺开始从底部向上填充凹槽，从而避免了空隙形成和回流焊料中形成的空气阱。 还描述了其它实施例。

公开(公告)号：US20090273082A1

公开(公告)日：2009-11-05

申请号：US12115254

申请日：2008-05-05

申请人： Suku Kim ,  James J. Murphy ,  Michael D. Gruenhagen ,  Matthew R. Reynolds ,  Romel N. Manatad ,  Jan Vincent Mancelita

发明人： Suku Kim ,  James J. Murphy ,  Michael D. Gruenhagen ,  Matthew R. Reynolds ,  Romel N. Manatad ,  Jan Vincent Mancelita

IPC分类号： H01L23/488 ,  H01L21/768

CPC分类号： H01L21/74 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.

摘要翻译： 描述了半导体器件中使用的晶片的局部变薄方法和由这些方法形成的结构。 该方法使半导体晶片的背面薄的局部区域形成具有在晶片（或管芯）内重复的双向通道设计的凹槽，使得没有直通道线穿过晶片（或管芯）。 双向图案设计保持通道不与晶片的晶体取向对齐。 然后通过将适当尺寸的焊球落入凹槽中然后通过焊球落下工艺填充凹陷，然后退火晶片以回流焊球并使其平坦化。 回流工艺开始从底部向上填充凹槽，从而避免了空隙形成和回流焊料中形成的空气阱。 还描述了其它实施例。

公开(公告)号：US20100164078A1

公开(公告)日：2010-07-01

申请号：US12347799

申请日：2008-12-31

申请人： Ruben Madrid ,  Romel N. Manatad ,  Maria Clemens Y. Quinones

发明人： Ruben Madrid ,  Romel N. Manatad ,  Maria Clemens Y. Quinones

IPC分类号： H01L23/34 ,  H01L21/56

CPC分类号： H01L23/49562 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor packages and methods for making and using such semiconductor packages are described. The semiconductor packages contain a dual gauge heat sink exposed on an upper part of the package, a leadframe containing a gate lead and an exposed drain pad on a lower part of the package, and a semiconductor die containing an IC device located between the heat sink and the leadframe. The gate of the IC device is connected to the gate lead of the leadframe using a bond interconnect wire or a gate interconnect clip located and placed under the heat sink and in between the heat sink and main leadframe. Such a configuration provides both a simple design for the semiconductor package and a simple method of manufacturing. Other embodiments are described.

摘要翻译： 描述了用于制造和使用这种半导体封装的半导体封装和方法。 半导体封装包含暴露在封装的上部的双规格散热器，在封装的下部包含栅极引线和暴露的漏极焊盘的引线框，以及包含位于散热器之间的IC器件的半导体管芯 和引线框架。 IC器件的栅极使用位于并放置在散热器下方并位于散热器和主引线框之间的接合互连线或栅极互连夹连接到引线框架的栅极引线。 这种配置提供了用于半导体封装的简单设计和简单的制造方法。 描述其他实施例。

公开(公告)号：US07586178B2

公开(公告)日：2009-09-08

申请号：US11689971

申请日：2007-03-22

申请人： Romel N. Manatad

发明人： Romel N. Manatad

IPC分类号： H01L23/495

CPC分类号： H01L23/49861 ,  H01L23/49844 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/40225 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01058 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/37099

摘要： A semiconductor package is disclosed. The package includes a leadframe structure comprising a die attach region and plurality of leads. A molding material is molded around at least a portion of the leadframe structure, and comprises a window. A semiconductor die comprising an edge is mounted on the die attach region and is within the window. A gap is present between the edge of the semiconductor die and the molding material.

摘要翻译： 公开了半导体封装。 封装包括引线框架结构，其包括管芯附接区域和多个引线。 围绕引线框架结构的至少一部分模制成型材料，并且包括窗口。 包括边缘的半导体管芯安装在管芯附接区域上并且在窗口内。 在半导体管芯的边缘和模制材料之间存在间隙。

公开(公告)号：US07560311B2

公开(公告)日：2009-07-14

申请号：US11446342

申请日：2006-06-01

申请人： Elsie Agdon Cabahug ,  Marvin Rosalejos Gestole ,  Margie Sebial Tumulak-Rios ,  Lilith U. Montayre ,  Romel N. Manatad

发明人： Elsie Agdon Cabahug ,  Marvin Rosalejos Gestole ,  Margie Sebial Tumulak-Rios ,  Lilith U. Montayre ,  Romel N. Manatad

IPC分类号： H01L21/50 ,  H01L23/495

CPC分类号： H01L23/49562 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.

摘要翻译： 公开了一种用于制造引线模制封装中的倒装芯片的方法。 在一些实施例中，该方法包括使用包括管芯附着区域和引线的引线框架结构。 管芯附着区域包括靠近引线的内部部分的凹陷和管芯附着区域中的孔。 半导体管芯安装到管芯附着区域。 成型材料通过孔并覆盖半导体管芯的第一表面和管芯附着区域。

公开(公告)号：US07154168B2

公开(公告)日：2006-12-26

申请号：US10702792

申请日：2003-11-05

申请人： Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

发明人： Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

IPC分类号： H01L23/495 ,  H01L23/498

CPC分类号： H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

公开(公告)号：US06943434B2

公开(公告)日：2005-09-13

申请号：US10678010

申请日：2003-10-02

申请人： Consuelo N. Tangpuz ,  Romel N. Manatad ,  Margie T. Rios ,  Erwin Victor R. Cruz

发明人： Consuelo N. Tangpuz ,  Romel N. Manatad ,  Margie T. Rios ,  Erwin Victor R. Cruz

IPC分类号： H01L21/60 ,  H01L23/31 ,  H01L23/485 ,  H01L23/495 ,  H01L23/544

CPC分类号： H01L23/49582 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49586 ,  H01L23/544 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18301 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/81205 ,  H01L2224/05599

摘要： A packaging assembly for semiconductor devices and a method for making such packaging is described. The invention provides a non-Pb bump design during a new flip-chip method of packaging. The design uses special conductive materials in a stud form, rather than a solder ball containing Pb. This configuration maintains a desirable solder thickness between the die and the leadframe and forms a high standoff by restricting solder wettabilty on the leadframe side. This configuration also absorbs any stress and protects the die from cracking. The invention also provides methods for making such semiconductor packages.

摘要翻译： 描述了一种用于半导体器件的封装组件及其制造方法。 本发明在新的倒装芯片封装方法中提供了非Pb凸点设计。 该设计采用螺柱形式的特殊导电材料，而不是含Pb的焊球。 该配置在管芯和引线框架之间保持期望的焊料厚度，并通过限制引线框架侧上的焊料润湿性而形成高的间隙。 这种结构也吸收任何应力并保护模具免受开裂。 本发明还提供了制造这种半导体封装的方法。

公开(公告)号：US07816784B2

公开(公告)日：2010-10-19

申请号：US12337513

申请日：2008-12-17

申请人： Joon-Seo Son ,  Romel N. Manatad ,  Armand Vincent Jereza

发明人： Joon-Seo Son ,  Romel N. Manatad ,  Armand Vincent Jereza

IPC分类号： H01L23/34

CPC分类号： H01L23/49524 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49562 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

摘要： Disclosed are PQFN semiconductor die packages for high-voltage, high-power applications, systems using the packages, and methods of making the packages. An exemplary package comprises a leadframe, a semiconductor die disposed on the leadframe, and a heat sink member disposed on the semiconductor die and the leadframe and integrated into the molding material of the package. The heat sink member has an electrically insulating substrate with a high breakdown voltage, and one or more conductive layers disposed on a first surface of the substrate that electrically interconnect the semiconductor to one or more leads of the leadframe.

摘要翻译： 公开了用于高电压，大功率应用的PQFN半导体管芯封装，使用封装的系统以及制造封装的方法。 示例性包装包括引线框架，设置在引线框架上的半导体管芯，以及设置在半导体管芯和引线框架上并集成到封装的成型材料中的散热构件。 散热构件具有具有高击穿电压的电绝缘衬底，以及设置在衬底的第一表面上的一个或多个导电层，其将半导体与引线框的一个或多个引线电连接。

公开(公告)号：US07816178B2

公开(公告)日：2010-10-19

申请号：US12499893

申请日：2009-07-09

申请人： Ruben P. Madrid ,  Romel N. Manatad

发明人： Ruben P. Madrid ,  Romel N. Manatad

IPC分类号： H01L21/00

CPC分类号： H01L23/49562 ,  H01L23/4334 ,  H01L24/17 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/17051 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.

摘要翻译： 发明要求保护的是具有双暴露表面的封装半导体器件和制造器件的方法。 热夹子和一个或多个源垫通过用于封装器件的非导电模制材料暴露在器件的相对两端。 热夹子和源垫可以是顶部或底部暴露的。 栅极，源极和漏极引线通过模制材料暴露，并且所有引线与底部暴露表面共面。 该器件可以具有多个半导体管芯或各种尺寸的管芯，同时仍然具有单一的，恒定的占地面积。 制造方法需要将半导体管芯附接到热夹子，然后将具有附接的热夹子的管芯附接到引线框架。 然后将所得到的器件依次模制，标记，修剪和分割，从而形成具有双暴露表面的封装半导体器件。