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公开(公告)号：US20190003884A1
公开(公告)日：2019-01-03
申请号：US16026476
申请日：2018-07-03
发明人： Takamitsu KITAMURA , Hideki Yagi
IPC分类号： G01J1/44 , G02B6/43 , G01J1/42 , H01L31/0232 , H01L31/0352 , H01L31/0304 , H01L31/109 , H01L31/18
摘要： A method for fabricating a light receiving device includes: preparing a first substrate product which includes a semiconductor region having a common semiconductor layer, a first semiconductor laminate for a photodiode, a second semiconductor laminate for a waveguide, and a butt-joint between the first semiconductor laminate and the second semiconductor laminate, the first laminate and the second semiconductor laminate being disposed on the common semiconductor layer; etching the first substrate product with a first mask to form a second substrate product having a photodiode mesa structure produced from the first semiconductor laminate and a preliminary mesa structure produced from the second semiconductor laminate; etching the second substrate product with the first mask and a second mask, formed on the photodiode mesa structure; to produce a waveguide mesa structure from the preliminary mesa structure, and the waveguide mesa structure having a height larger than that of the preliminary mesa structure.
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2.发明授权Integrated optical semiconductor device and integrated optical semiconductor device assembly 有权集成光半导体器件和集成光半导体器件组件公开(公告)号：US09366835B2
公开(公告)日：2016-06-14
申请号：US14643951
申请日：2015-03-10
发明人： Ryuji Masuyama , Yoshihiro Yoneda , Hideki Yagi , Naoko Konishi
CPC分类号： G02B6/4274 , G02B6/12004 , G02B6/122 , G02B6/131 , G02B6/136 , G02B6/2813 , G02B6/4204 , G02B6/428 , G02B6/4295
摘要： An integrated optical semiconductor device includes a substrate including first and second regions; a plurality of light receiving devices disposed in the second region; a multimode interference coupler disposed in the first region, the multimode interference coupler including output optical waveguides optically coupled to the corresponding light receiving devices; first and second conductive layers disposed on a back surface of the substrate in the first and second regions, respectively; and a plurality of capacitors disposed in the second region, each of the capacitors including a first electrode connected to one of the light receiving devices and a second electrode connected to the second conductive layer. The second conductive layer is electrically insulated from the first conductive layer. The substrate is made of a semi-insulating semiconductor. The multimode interference coupler and the light receiving devices include the same n-type semiconductor layer disposed on a principal surface of the substrate.
摘要翻译： 一种集成光学半导体器件，包括：包括第一和第二区域的衬底; 设置在所述第二区域中的多个光接收装置; 设置在所述第一区域中的多模干涉耦合器，所述多模干涉耦合器包括光耦合到相应的光接收装置的输出光波导; 分别设置在第一和第二区域中的基板的背面上的第一和第二导电层; 以及设置在第二区域中的多个电容器，每个电容器包括连接到一个光接收装置的第一电极和连接到第二导电层的第二电极。 第二导电层与第一导电层电绝缘。 基板由半绝缘半导体制成。 多模干涉耦合器和光接收装置包括设置在基板的主表面上的相同的n型半导体层。
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公开(公告)号：US09176360B2
公开(公告)日：2015-11-03
申请号：US14331762
申请日：2014-07-15
发明人： Hideki Yagi , Naoko Konishi , Takamitsu Kitamura , Naoya Kono
CPC分类号： G02F1/2257 , G02B6/1228 , G02F2001/212 , G02F2001/217
摘要： A method for producing a spot-size convertor includes the steps of preparing a substrate; forming a stacked semiconductor layer including first and second core layers on the substrate; forming a mesa structure by etching the stacked semiconductor layer using a first mask, the mesa structure including a side surface and a bottom portion of the first core layer; forming a protective mask covering the side surface; etching the bottom portion using the protective mask to form a top mesa; and forming a bottom mesa by etching the second core layer using a second mask. The top mesa includes the first core layer and a portion having a mesa width gradually reduced in a first direction of a waveguide axis. The bottom mesa includes the second core layer and a portion having a mesa width gradually reduced in a second direction opposite to the first direction.
摘要翻译： 一种点尺寸转换器的制造方法包括准备基板的工序; 在所述基板上形成包括第一和第二芯层的层叠半导体层; 通过使用第一掩模蚀刻所述堆叠半导体层来形成台面结构，所述台面结构包括所述第一芯层的侧表面和底部; 形成覆盖所述侧面的保护罩; 使用防护罩蚀刻底部以形成顶部台面; 以及通过使用第二掩模蚀刻所述第二芯层来形成底台面。 顶部台面包括第一芯层和沿波导轴的第一方向逐渐减小的台面宽度的部分。 底部台面包括第二芯层和在与第一方向相反的第二方向上逐渐减小的台面宽度的部分。
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公开(公告)号：US08986553B2
公开(公告)日：2015-03-24
申请号：US13935704
申请日：2013-07-05
发明人： Takamitsu Kitamura , Hideki Yagi
CPC分类号： B29D11/00673 , G02F1/2257 , G02F2001/212
摘要： A method for manufacturing an optical semiconductor device includes the steps of preparing a substrate product including a semiconductor layer, a mesa structure, and a protective layer; forming a buried layer composed of a resin on the substrate product; forming a first opening in the buried layer on the mesa structure; forming a second opening in the buried layer on the semiconductor layer; exposing the mesa structure and the semiconductor layer by etching the protective layer; forming a first electrode in the first opening; and forming a second electrode in the second opening. The step of forming the second opening includes a first etching step including etching the buried layer using a first resist mask for forming a recess and a second etching step including etching the buried layer using a second resist mask having an opening pattern which has an opening width not smaller than that of the recess.
摘要翻译： 一种光半导体装置的制造方法，其特征在于，包括：准备包括半导体层，台面结构和保护层的基板制品的工序; 在所述基板产品上形成由树脂构成的掩埋层; 在台面结构的埋层中形成第一开口; 在所述半导体层上的所述掩埋层中形成第二开口; 通过蚀刻保护层来暴露台面结构和半导体层; 在第一开口中形成第一电极; 以及在所述第二开口中形成第二电极。 形成第二开口的步骤包括：第一蚀刻步骤，包括使用用于形成凹部的第一抗蚀剂掩模蚀刻掩埋层;以及第二蚀刻步骤，包括使用具有开口图案的第二抗蚀剂掩模蚀刻所述掩埋层，所述第二抗蚀剂掩模具有开口宽度 不小于休息区。
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公开(公告)号：US08811444B2
公开(公告)日：2014-08-19
申请号：US13733264
申请日：2013-01-03
发明人： Hideki Yagi
CPC分类号： H01S5/3013 , B82Y20/00 , G02B6/12004 , H01S5/026 , H01S5/0265 , H01S5/1017 , H01S5/1032 , H01S5/12 , H01S5/2213 , H01S5/2224 , H01S5/2275 , H01S5/3213 , H01S5/34306
摘要： A semiconductor integrated device includes a light-emitting portion including a first lower mesa, a first lower buried layer provided on a side surface of the first lower mesa, a first upper mesa provided above the first lower mesa, and a first upper buried layer provided on a side surface of the first upper mesa; and an optical modulator portion including a second lower mesa, a second lower buried layer provided on a side surface of the second lower mesa, a second upper mesa provided above the second lower mesa, and a second upper buried layer provided on a side surface of the second upper mesa. The first and second lower mesas include first and second core layers optically coupled to each other. The first and second lower buried layers are composed of a semi-insulating semiconductor. The first and second upper buried layers are composed of a resin material.
摘要翻译： 半导体集成器件包括：第一下台面的发光部，设置在第一下台面的侧面的第一下掩埋层，设置在第一下台面的第一上台面;以及第一上掩埋层， 在第一上台面的侧面上; 以及包括第二下台面的光调制器部分，设置在第二下台面的侧表面上的第二下掩埋层，设置在第二下台面上方的第二上台面，以及设置在第二下台面的侧表面上的第二上掩埋层 第二个上部台面 第一和第二下台面包括彼此光耦合的第一和第二芯层。 第一和第二下埋层由半绝缘半导体构成。 第一和第二上埋层由树脂材料构成。
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公开(公告)号：US11231552B2
公开(公告)日：2022-01-25
申请号：US17150791
申请日：2021-01-15
发明人： Takuya Okimoto , Hideki Yagi
摘要： A photo detector includes a variable optical attenuator provided on a substrate, an optical 90-degree hybrid device provided on the substrate, and a plurality of photodiodes provided on the substrate. The plurality of photodiodes are optically coupled to the variable optical attenuator via the optical 90-degree hybrid device. The variable optical attenuator includes an optical waveguide disposed on the substrate, a heater configured to heat the optical waveguide, and an insulating layer at least partially disposed between the substrate and the optical waveguide.
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7.发明授权Semiconductor optical modulator and method for manufacturing semiconductor optical modulator 有权半导体光调制器及制造半导体光调制器的方法公开(公告)号：US09523871B2
公开(公告)日：2016-12-20
申请号：US14796770
申请日：2015-07-10
CPC分类号： G02F1/025 , G02F1/218 , G02F1/2255
摘要： A semiconductor optical modulator includes a substrate having a principal surface; a waveguide disposed on the principal surface of the substrate, the waveguide extending in a first direction; a first electrode disposed on the waveguide, the first electrode being in contact with an upper surface of the waveguide; a first wiring connected to the first electrode, the first wiring extending in a second direction intersecting the first direction; a build-up portion connected to the first wiring; a second wiring connected to the build-up portion, the second wiring extending in a plane parallel to the principal surface of the substrate; and a resin layer disposed on the substrate, the resin layer embedding the first wiring and the build-up portion. The build-up portion extends along a third direction, the third direction intersecting perpendicularly to the principal surface of the substrate. The second wiring is disposed on the resin layer.
摘要翻译： 半导体光调制器包括具有主表面的基板; 布置在所述基板的主表面上的波导，所述波导沿第一方向延伸; 设置在所述波导上的第一电极，所述第一电极与所述波导的上表面接触; 连接到所述第一电极的第一布线，所述第一布线沿与所述第一方向相交的第二方向延伸; 连接到第一布线的积聚部分; 连接到所述积聚部分的第二布线，所述第二布线在平行于所述基板的主表面的平面中延伸; 以及设置在基板上的树脂层，树脂层嵌入第一布线和积层部。 堆积部分沿着第三方向延伸，第三方向垂直于衬底的主表面相交。 第二布线设置在树脂层上。
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公开(公告)号：US09329451B2
公开(公告)日：2016-05-03
申请号：US14605578
申请日：2015-01-26
发明人： Takamitsu Kitamura , Hideki Yagi
IPC分类号： H01L21/302 , G02F1/225 , G06F17/50 , H01L21/66 , H01L21/311 , H01L33/44 , G02F1/025 , G02B6/136 , G02B6/12 , G02F1/21
CPC分类号： G02F1/2257 , G02B6/136 , G02B2006/121 , G02B2006/12173 , G02F1/025 , G02F2001/212 , G06F17/5068 , H01L21/31116 , H01L22/12 , H01L22/20 , H01L33/44
摘要： A method for producing optical semiconductor devices includes: forming a stacked semiconductor layer on a device substrate to provide an epitaxial substrate having a size corresponding to a section arrangement; forming, on the epitaxial substrate, a mask having a pattern for a semiconductor mesa and for a trench of at least one optical semiconductor device, a width of the trench in the pattern being determined according to a trench width map in which trench width is based upon an in-plane distribution of the thickness of a resin layer of the at least one device, and upon a correlation between the thickness of the resin layer and the trench width; forming a trench structure including the semiconductor mesa and the trench by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer.
摘要翻译： 一种用于制造光学半导体器件的方法包括：在器件衬底上形成堆叠的半导体层以提供具有对应于部分布置的尺寸的外延衬底; 在所述外延衬底上形成具有用于半导体台面的图案和至少一个光学半导体器件的沟槽的掩模，所述图案中的沟槽的宽度根据沟槽宽度基于的沟槽宽度图确定 在所述至少一个装置的树脂层的厚度的面内分布中，以及所述树脂层的厚度和所述沟槽宽度之间的相关性; 通过使用掩模蚀刻堆叠的半导体层来形成包括半导体台面和沟槽的沟槽结构; 在沟槽结构上形成树脂层; 并通过蚀刻树脂层在半导体台面上形成开口。
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公开(公告)号：US20140342491A1
公开(公告)日：2014-11-20
申请号：US14280043
申请日：2014-05-16
发明人： Ryuji Masuyama , Yoshihiro Yoneda , Hideki Yagi , Naoko Konishi
IPC分类号： G02B6/13
CPC分类号： G02B6/131 , G02B2006/12173 , G02B2006/12178
摘要： A method for manufacturing a waveguide-type semiconductor device includes the steps of forming an epitaxial structure including a waveguide mesa and a device mesa; forming a mask for selective growth on the epitaxial structure; growing a semiconductor region on an end surface of the device mesa by using the mask for selective growth, the semiconductor region including a side portion having a layer shape and a protruding wall portion; forming an ohmic electrode on a top surface of the device mesa; forming a resin layer on the device mesa and the semiconductor region; forming a resin mask having an opening on the ohmic electrode; forming an electric conductor connecting the ohmic electrode to an electrode pad, the electric conductor passing over the protruding wall portion while making contact with a surface of the resin mask; and removing the resin mask after forming the electric conductor.
摘要翻译： 制造波导型半导体器件的方法包括以下步骤：形成包括波导台面和器件台面的外延结构; 在外延结构上形成用于选择性生长的掩模; 通过使用用于选择性生长的掩模在器件台面的端面上生长半导体区域，该半导体区域包括具有层状的侧部和突出的壁部; 在器件台面的顶表面上形成欧姆电极; 在器件台面和半导体区域上形成树脂层; 形成在所述欧姆电极上具有开口的树脂掩模; 形成将所述欧姆电极与电极焊盘连接的电导体，所述电导体在与所述树脂掩模的表面接触的同时越过所述突出壁部; 并在形成电导体之后去除树脂掩模。
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公开(公告)号：US12044569B2
公开(公告)日：2024-07-23
申请号：US18124952
申请日：2023-03-22
发明人： Takuya Okimoto , Hideki Yagi , Takuya Mitarai
IPC分类号： G01J1/44
CPC分类号： G01J1/44 , G01J2001/446
摘要： A light receiving device includes a semiconductor substrate having a first major surface and a second major surface opposite to the first major surface, and a metal pattern layer provided on the second major surface. The first major surface is provided with a first input port configured to receive an input of signal light, a second input port configured to receive an input of local oscillation light, a first light receiving element optically coupled to the first input port, an optical 90 degree hybrid element optically coupled to the first input port and the second input port, and a second light receiving element optically coupled to the optical 90 degree hybrid element. The metal pattern layer contains at least one of titanium or chromium.
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