公开(公告)号：US08450788B2

公开(公告)日：2013-05-28

申请号：US13300818

申请日：2011-11-21

申请人： Sun-Il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

发明人： Sun-Il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

IPC分类号： H01L29/76

CPC分类号： H01L27/1158 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

摘要： A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

公开(公告)号：US20120061741A1

公开(公告)日：2012-03-15

申请号：US13300818

申请日：2011-11-21

申请人： Sun-Il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

发明人： Sun-Il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

IPC分类号： H01L29/78

CPC分类号： H01L27/1158 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

摘要： A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

摘要翻译： 垂直NAND闪速存储器件包括在衬底上具有面和串联的闪存单元串的衬底。 第一闪存单元与面相邻，并且最后的闪存单元远离面。 闪存单元包括堆叠在表面上的重复层图案和延伸穿过一系列重复层图案的柱。 支柱包括至少一个斜壁。 串中重复层图案的系列中的至少两个具有不同的厚度。 还描述了其它垂直微电子器件和相关的制造方法。

公开(公告)号：US20100078701A1

公开(公告)日：2010-04-01

申请号：US12420518

申请日：2009-04-08

申请人： Sun-Il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

发明人： Sun-Il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

IPC分类号： H01L29/788 ,  H01L29/66

CPC分类号： H01L27/1158 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

摘要： A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

摘要翻译： 垂直NAND闪速存储器件包括在衬底上具有面和串联的闪存单元串的衬底。 第一闪存单元与面相邻，并且最后的闪存单元远离面。 闪存单元包括堆叠在表面上的重复层图案和延伸穿过一系列重复层图案的柱。 支柱包括至少一个斜壁。 串中重复层图案的系列中的至少两个具有不同的厚度。 还描述了其它垂直微电子器件和相关的制造方法。

公开(公告)号：US08084805B2

公开(公告)日：2011-12-27

申请号：US12420518

申请日：2009-04-08

申请人： Sun-Il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

发明人： Sun-Il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

IPC分类号： H01L29/76

CPC分类号： H01L27/1158 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

摘要： A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

摘要翻译： 垂直NAND闪速存储器件包括在衬底上具有面和串联的闪存单元串的衬底。 第一闪存单元与面相邻，并且最后的闪存单元远离面。 闪存单元包括堆叠在表面上的重复层图案和延伸穿过一系列重复层图案的柱。 支柱包括至少一个斜壁。 串中重复层图案的系列中的至少两个具有不同的厚度。 还描述了其它垂直微电子器件和相关的制造方法。

公开(公告)号：US07696556B2

公开(公告)日：2010-04-13

申请号：US11518724

申请日：2006-09-11

申请人： Sung-Hoi Hur ,  Young-Min Park ,  Sang-Bin Song ,  Min-Cheol Park ,  Ji-Hwon Lee ,  Su-Youn Yi ,  Jang-Min Yoo

发明人： Sung-Hoi Hur ,  Young-Min Park ,  Sang-Bin Song ,  Min-Cheol Park ,  Ji-Hwon Lee ,  Su-Youn Yi ,  Jang-Min Yoo

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L29/7887 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529

摘要： High-voltage MOS transistors with a floated drain-side auxiliary gate are provided. The high-voltage MOS transistors include a source region and a drain region provided in a semiconductor substrate. A main gate electrode is disposed over the semiconductor substrate between the drain region and the source region. A lower drain-side auxiliary gate and an upper drain-side auxiliary gate are sequentially stacked over the semiconductor substrate between the main gate electrode and the drain region. The lower drain-side auxiliary gate is electrically insulated from the semiconductor substrate, the main gate electrode and the upper drain-side auxiliary gate. Methods of fabricating the high-voltage MOS transistors are also provided.

摘要翻译： 提供了具有浮置漏极侧辅助栅极的高压MOS晶体管。 高压MOS晶体管包括设置在半导体衬底中的源极区域和漏极区域。 主栅极设置在漏区和源区之间的半导体衬底之上。 下侧漏极侧辅助栅极和上部漏极侧辅助栅极依次堆叠在主栅极和漏极区域之间的半导体衬底上。 下漏极侧辅助栅极与半导体基板，主栅电极和上漏极侧辅助栅极电绝缘。 还提供了制造高压MOS晶体管的方法。

公开(公告)号：US20070063257A1

公开(公告)日：2007-03-22

申请号：US11518724

申请日：2006-09-11

申请人： Sung-Hoi Hur ,  Young-Min Park ,  Sang-Bin Song ,  Min-Cheol Park ,  Ji-Hwon Lee ,  Su-Youn Yi ,  Jang-Min Yoo

发明人： Sung-Hoi Hur ,  Young-Min Park ,  Sang-Bin Song ,  Min-Cheol Park ,  Ji-Hwon Lee ,  Su-Youn Yi ,  Jang-Min Yoo

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L29/7887 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529

摘要： High-voltage MOS transistors with a floated drain-side auxiliary gate are provided. The high-voltage MOS transistors include a source region and a drain region provided in a semiconductor substrate. A main gate electrode is disposed over the semiconductor substrate between the drain region and the source region. A lower drain-side auxiliary gate and an upper drain-side auxiliary gate are sequentially stacked over the semiconductor substrate between the main gate electrode and the drain region. The lower drain-side auxiliary gate is electrically insulated from the semiconductor substrate, the main gate electrode and the upper drain-side auxiliary gate. Methods of fabricating the high-voltage MOS transistors are also provided.

摘要翻译： 提供了具有浮置漏极侧辅助栅极的高压MOS晶体管。 高压MOS晶体管包括设置在半导体衬底中的源极区域和漏极区域。 主栅极设置在漏区和源区之间的半导体衬底之上。 下侧漏极侧辅助栅极和上部漏极侧辅助栅极依次堆叠在主栅极和漏极区域之间的半导体衬底上。 下漏极侧辅助栅极与半导体基板，主栅电极和上漏极侧辅助栅极电绝缘。 还提供了制造高压MOS晶体管的方法。

公开(公告)号：US20140124846A1

公开(公告)日：2014-05-08

申请号：US14154834

申请日：2014-01-14

申请人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

发明人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

IPC分类号： H01L27/02

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

摘要翻译： 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

公开(公告)号：US08319275B2

公开(公告)日：2012-11-27

申请号：US12698542

申请日：2010-02-02

申请人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

发明人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L27/088

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

摘要翻译： 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

公开(公告)号：US20110305083A1

公开(公告)日：2011-12-15

申请号：US13217627

申请日：2011-08-25

申请人： Sunil Shim ,  Sunghoi Hur ,  Younggoan Jang ,  Jinho Kim ,  Su-Youn Yi ,  HuiChang Moon

发明人： Sunil Shim ,  Sunghoi Hur ,  Younggoan Jang ,  Jinho Kim ,  Su-Youn Yi ,  HuiChang Moon

IPC分类号： G11C11/34

CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C8/14 ,  G11C16/0483 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578

摘要： A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting the second word lines. Each of the first connection lines connects the first word lines located at a common layer, each of the second connection lines connects the second word lines located at a common layer and at least one second word line stack is disposed between a pair of the first word line stacks.

摘要翻译： 具有三维结构的非易失性存储器件包括第一字线堆叠，其中第一字线被堆叠; 第二字线堆叠，其中平行于第一字线的第二字线被堆叠; 连接第一字线的第一连接线; 以及连接第二字线的第二连接线。 每个第一连接线连接位于公共层的第一字线，每个第二连接线连接位于公共层的第二字线，并且至少一个第二字线堆叠设置在一对第一字之间 线堆叠

公开(公告)号：US09012977B2

公开(公告)日：2015-04-21

申请号：US14154834

申请日：2014-01-14

申请人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

发明人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L27/02 ,  H01L27/115

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

摘要翻译： 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。