公开(公告)号：US06916729B2

公开(公告)日：2005-07-12

申请号：US10409516

申请日：2003-04-08

申请人： Sunfei Fang ,  Keith Kwong Hon Wong ,  Paul D. Agnello ,  Christian Lavoie ,  Lawrence A. Clevenger ,  Chester T. Dziobkowski ,  Richard J. Murphy ,  Patrick W. DeHaven ,  Nivo Rovedo ,  Hsiang-Jen Huang

发明人： Sunfei Fang ,  Keith Kwong Hon Wong ,  Paul D. Agnello ,  Christian Lavoie ,  Lawrence A. Clevenger ,  Chester T. Dziobkowski ,  Richard J. Murphy ,  Patrick W. DeHaven ,  Nivo Rovedo ,  Hsiang-Jen Huang

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

摘要： A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

摘要翻译： 在半导体器件上形成硅化物的方法包括在衬底的硅区域上沉积第一难熔金属层，在第一耐火金属层上沉积近贵金属层，以及在第二耐火金属层的近旁沉积第二难熔金属层， 贵金属层。 半导体器件在第一退火工艺中退火以形成邻接半导体器件的掺杂区域的硅化物层。 除去近贵金属层和第二难熔金属层的未反应部分。 该器件可以在任选的第二退火工艺中进行退火，以将硅化物层转换成低电阻相位硅化物材料。 通过本发明的实施例使结漏电和桥接最小化或消除，并且实现更平滑的硅化表面。

公开(公告)号：US07223691B2

公开(公告)日：2007-05-29

申请号：US10965031

申请日：2004-10-14

申请人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Patrick W. DeHaven ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Terry A. Spooner ,  Tsong-Lin L. Tai ,  Kwong Hon Wong ,  Chin-Chao Yang

发明人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Patrick W. DeHaven ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Terry A. Spooner ,  Tsong-Lin L. Tai ,  Kwong Hon Wong ,  Chin-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76888

摘要： A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.

摘要翻译： 具有低接触电阻和改进的可靠性的新颖的层间接触通孔结构以及形成接触通孔的方法。 该方法包括以下步骤：通过层间电介质层蚀刻开口以暴露下面的金属（铜）层表面; 并且将惰性气体（氮气）的低能量离子注入进入下面暴露的金属; 并且将耐火衬垫沉积到壁和底部通孔结构中，由于进行的惰性气体注入的存在而将具有较低的接触电阻。 优选地，惰性氮气与下面暴露的铜金属反应形成一层薄的CuN。

公开(公告)号：US07112481B2

公开(公告)日：2006-09-26

申请号：US11254929

申请日：2005-10-20

申请人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

发明人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

摘要翻译： 一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在用于容纳第一类型半导体器件的半导体衬底中形成第一阱区; 在所述半导体衬底中形成用于容纳第二类型半导体器件的第二阱区; 用掩模屏蔽第一类型半导体器件; 在所述第二类型半导体器件上沉积第一金属层; 在所述第二类型半导体器件上执行第一自对准硅化物形成; 去除面膜; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及在所述第一类型半导体器件上执行第二自对准硅化物形成。 该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同硅化物材料的工艺。

公开(公告)号：US07067368B1

公开(公告)日：2006-06-27

申请号：US11254934

申请日：2005-10-20

申请人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

发明人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

公开(公告)号：US07064025B1

公开(公告)日：2006-06-20

申请号：US10904884

申请日：2004-12-02

申请人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

发明人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

公开(公告)号：US07122472B2

公开(公告)日：2006-10-17

申请号：US10904885

申请日：2004-12-02

申请人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Christian Lavoie ,  Clement H. Wann

发明人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Christian Lavoie ,  Clement H. Wann

IPC分类号： H01L21/44

CPC分类号： H01L21/823835

摘要： A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.

摘要翻译： 一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅的方法，其中所述方法包括在半导体衬底中形成具有第一阱区的第一类型半导体器件，其中第一源极/漏极硅化物区域 第一阱区域和从第一源极/漏极硅化物区域隔离的第一类型栅极; 形成在所述半导体衬底中具有第二阱区域的第二类型半导体器件，所述第二阱区域中的第二源极/漏极硅化物区域和与所述第二源极/漏极硅化物区域隔离的第二类型栅极; 在所述第二类型半导体器件上选择性地形成第一金属层; 仅在第二型栅极上执行第一完全硅化（FUSI）栅极形成; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及仅在第一类型栅极上执行第二FUSI栅极形成。

公开(公告)号：US07785999B2

公开(公告)日：2010-08-31

申请号：US11830277

申请日：2007-07-30

申请人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

发明人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

IPC分类号： H01L21/44 ,  H01L21/8242

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823443 ,  H01L29/66545

摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

摘要翻译： 提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。

公开(公告)号：US07271455B2

公开(公告)日：2007-09-18

申请号：US10890753

申请日：2004-07-14

申请人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

发明人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823443 ,  H01L29/66545

摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

摘要翻译： 提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。

公开(公告)号：US07785950B2

公开(公告)日：2010-08-31

申请号：US11164114

申请日：2005-11-10

申请人： Sunfei Fang ,  Jun Jung Kim ,  Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Young Way Teh

发明人： Sunfei Fang ,  Jun Jung Kim ,  Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Young Way Teh

IPC分类号： H01L21/8238 ,  H01L21/469

CPC分类号： H01L21/823864 ,  H01L21/823807

摘要： A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

摘要翻译： 公开了一种在包括nFET和PFET以及相关结构的半导体器件中提供双重应力记忆技术的方法。 该方法的一个实施例包括在nFET上形成拉伸应力层，并在pFET上形成压应力层，退火以在半导体器件中记忆应力并去除应力层。 压应力层可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。 退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET中。

公开(公告)号：US20070105299A1

公开(公告)日：2007-05-10

申请号：US11164114

申请日：2005-11-10

申请人： Sunfei Fang ,  Jun Kim ,  Zhijiong Luo ,  Hung Ng ,  Nivo Rovedo ,  Young Teh

发明人： Sunfei Fang ,  Jun Kim ,  Zhijiong Luo ,  Hung Ng ,  Nivo Rovedo ,  Young Teh

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/823807

摘要： A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

摘要翻译： 公开了一种在包括nFET和PFET以及相关结构的半导体器件中提供双重应力记忆技术的方法。 该方法的一个实施例包括在nFET上形成拉伸应力层，并在pFET上形成压应力层，退火以在半导体器件中记忆应力并去除应力层。 压应力层可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。 退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET中。