利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.024 秒)

    DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE
    1.
    发明申请
    DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE 有权
    双应力记忆技术方法及相关结构

    公开(公告)号：US20070105299A1

    公开(公告)日：2007-05-10

    申请号：US11164114

    申请日：2005-11-10

    申请人： Sunfei Fang ,  Jun Kim ,  Zhijiong Luo ,  Hung Ng ,  Nivo Rovedo ,  Young Teh

    发明人： Sunfei Fang ,  Jun Kim ,  Zhijiong Luo ,  Hung Ng ,  Nivo Rovedo ,  Young Teh

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823864 ,  H01L21/823807

    摘要： A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

    摘要翻译： 公开了一种在包括nFET和PFET以及相关结构的半导体器件中提供双重应力记忆技术的方法。 该方法的一个实施例包括在nFET上形成拉伸应力层，并在pFET上形成压应力层，退火以在半导体器件中记忆应力并去除应力层。 压应力层可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。 退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET中。

    Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance
    6.
    发明申请
    Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance 有权
    在晶体管栅极结构上使用耐蚀刻衬里以实现高器件性能的方法和结构

    公开(公告)号：US20060145275A1

    公开(公告)日：2006-07-06

    申请号：US11369409

    申请日：2006-03-07

    申请人： Hung Ng ,  Haining Yang

    发明人： Hung Ng ,  Haining Yang

    IPC分类号： H01L29/94 ,  H01L29/76

    CPC分类号： H01L29/665 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/0629 ,  H01L29/6656

    摘要： An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location of silicide formation within source and drain regions within the substrate at the base of the transistor gate stack. The liner also covers a resistor gate stack preventing silicide formation within or adjacent to the resistor gate stack.

    摘要翻译： 覆盖晶体管栅极叠层的侧壁并且沿晶体管栅极堆叠的基极的衬底的一部分覆盖的耐蚀刻衬里。 衬垫防止在栅极堆叠的侧壁上形成硅化物，这可能产生电短路，并且确定在晶体管栅极堆叠的基极处的衬底内的源极和漏极区域内的硅化物形成的位置。 衬套还覆盖阻止在电阻器栅极叠层内或邻近电阻器栅叠层形成硅化物的电阻器栅极堆叠。

    Process for defining a pattern using an anti-reflective coating and structure therefor
    7.
    发明授权
    Process for defining a pattern using an anti-reflective coating and structure therefor 失效
    使用抗反射涂层定义图案的方法及其结构

    公开(公告)号：US06030541A

    公开(公告)日：2000-02-29

    申请号：US100542

    申请日：1998-06-19

    申请人： James W. Adkisson ,  Michael Caterer ,  James T. Marsh ,  Hung Ng ,  James M. Oberschmidt ,  Jed H. Rankin

    发明人： James W. Adkisson ,  Michael Caterer ,  James T. Marsh ,  Hung Ng ,  James M. Oberschmidt ,  Jed H. Rankin

    IPC分类号： H01L21/027 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/033

    CPC分类号： H01L21/0276 ,  H01L21/28123 ,  H01L21/32139

    摘要： A pattern in a surface is defined by providing on the surface a hard mask material; depositing an anti-reflective coating on the hard mask material; applying a photoresist layer on the anti-reflective coating; patterning the photoresist layer, anti-reflective layer and hard mask material; and removing the remaining portions of the photoresist layer and anti-reflective layer; and then patterning the substrate using the hard mask as the mask. Also provided is a structure for defining a pattern in a surface which comprises a surface having a hard mask material thereon; an anti-reflective coating located on the hard mask material; and a photoresist located on the anti-reflective coating. Also provided is an etchant composition for removing the hard mask material which comprises an aqueous composition of HF and chlorine.

    摘要翻译： 通过在表面上提供硬掩模材料来限定表面中的图案; 在所述硬掩模材料上沉积抗反射涂层; 在抗反射涂层上施加光致抗蚀剂层; 图案化光致抗蚀剂层，抗反射层和硬掩模材料; 并除去光致抗蚀剂层和抗反射层的剩余部分; 然后使用硬掩模作为掩模来图案化衬底。 还提供了一种用于在表面上限定图案的结构，其包括其上具有硬掩模材料的表面; 位于硬掩模材料上的抗反射涂层; 以及位于抗反射涂层上的光致抗蚀剂。 还提供了用于除去硬掩模材料的蚀刻剂组合物，其包含HF和氯的水性组合物。

    METHOD AND STRUCTURE TO USE AN ETCH RESISTANT LINER ON TRANSISTOR GATE STRUCTURE TO ACHIEVE HIGH DEVICE PERFORMANCE
    9.
    发明申请
    METHOD AND STRUCTURE TO USE AN ETCH RESISTANT LINER ON TRANSISTOR GATE STRUCTURE TO ACHIEVE HIGH DEVICE PERFORMANCE 审中-公开
    在晶体闸门结构上使用耐蚀衬层以达到高设备性能的方法和结构

    公开(公告)号：US20080036017A1

    公开(公告)日：2008-02-14

    申请号：US11836193

    申请日：2007-08-09

    申请人： Hung Ng ,  Haining Yang

    发明人： Hung Ng ,  Haining Yang

    IPC分类号： H01L31/00

    CPC分类号： H01L29/665 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/0629 ,  H01L29/6656

    摘要： A semiconductor device. The semiconductor device includes a substrate includes: a substrate having a first gate stack on a surface of the substrate, wherein the first gate stack has a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate; an etch resistant first liner over the sidewalls of the first gate stack and not over the top surface of the first gate stack; a first outer spacer over the first liner, wherein the first liner is disposed between the first outer spacer and the sidewalls of the first gate stack, and wherein a portion of the first liner covers a first portion of the surface of the substrate; an insulative layer on a second portion of the surface of the substrate; and a conductive layer on the top surface of the first gate stack.

    摘要翻译： 半导体器件。 该半导体器件包括：衬底，其包括：在衬底的表面上具有第一栅极堆叠的衬底，其中第一栅极堆叠具有平行于衬底的表面的顶表面和垂直于衬底表面的侧壁; 在第一栅极堆叠的侧壁上并且不在第一栅极堆叠的顶表面上的耐蚀刻的第一衬垫; 在所述第一衬垫上方的第一外隔离物，其中所述第一衬垫设置在所述第一外隔离物和所述第一栅叠层的侧壁之间，并且其中所述第一衬垫的一部分覆盖所述衬底的所述表面的第一部分; 在所述基板的表面的第二部分上的绝缘层; 以及在第一栅极堆叠的顶表面上的导电层。