公开(公告)号：US20150179816A1

公开(公告)日：2015-06-25

申请号：US14135142

申请日：2013-12-19

申请人： JACOB T. WILLIAMS ,  Cheong Min Hong ,  Sung-Taeg Kang ,  David G. Kolar ,  Jane A. Yater

发明人： JACOB T. WILLIAMS ,  Cheong Min Hong ,  Sung-Taeg Kang ,  David G. Kolar ,  Jane A. Yater

IPC分类号： H01L29/792 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/66

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.

摘要翻译： 形成闪存单元的方法包括在基板上形成第一硬掩模和第二硬掩模。 选择栅极形成为围绕第一硬掩模的间隔物。 在第一和第二硬掩模和选择栅极上形成电荷存储层。 控制栅极形成为围绕第二硬掩模的间隔物。 控制栅极中的凹槽填充有电介质材料。 凹槽形成在控制栅极的弯曲侧壁和电荷存储层的与控制栅极的弯曲侧壁直接相邻的侧壁之间。

公开(公告)号：US09006093B2

公开(公告)日：2015-04-14

申请号：US13928666

申请日：2013-06-27

申请人： Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

发明人： Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC分类号： H01L29/792 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.

摘要翻译： 制造半导体结构的方法包括在衬底上形成选择栅叠层。 衬底包括非易失性存储器（NVM）区域和高电压区域。 选择栅极堆叠形成在NVM区域中。 电荷存储层形成在衬底的NVM区域和高电压区域上。 电荷存储层包括在介电材料的底层和电介质材料的顶层之间的电荷存储材料。 在NVM区域中的电荷存储材料保持未氧化的同时，高压区域中的电荷存储材料被氧化。

公开(公告)号：US08877585B1

公开(公告)日：2014-11-04

申请号：US13969180

申请日：2013-08-16

申请人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang

发明人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/11546 ,  H01L29/42332 ,  H01L29/66825

摘要： A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. A memory cell is fabricated in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The first conductive layer is patterned to form transistor gates in the first and second high voltage portions. A protective mask is formed over the NVM portion and the first and second high voltage portions. A transistor gate is formed in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.

摘要翻译： 使用具有非易失性存储器（NVM）部分，第一高压部分，第二高压部分和逻辑部分的衬底制造半导体结构的方法包括在主要的氧化物层上形成第一导电层 NVM部分中的衬底表面，第一和第二高压部分以及逻辑部分。 在NVM部分中制造存储单元，同时第一导电层保留在第一和第二高压部分和逻辑部分中。 图案化第一导电层以在第一和第二高压部分中形成晶体管栅极。 在NVM部分和第一和第二高压部分上形成保护掩模。 晶体管栅极形成在逻辑部分中，同时保护掩模保留在NVM部分以及第一和第二高电压部分中。

公开(公告)号：US20140209995A1

公开(公告)日：2014-07-31

申请号：US13753047

申请日：2013-01-29

申请人： Cheong Min Hong ,  Sung-Taeg Kang

发明人： Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： Non-volatile memory (NVM) cells having carbon impurities are disclosed along with related manufacturing methods. The carbon impurities can be introduced using a variety of techniques, including through epitaxial growth of silicon-carbon (SiC) layers and/or carbon implants. Further, the carbon impurities can be introduced into one or more structures within NVM cells, including source regions, drain regions, gate regions, and/or charge storage layers. For discrete charge storage layers that utilize nanocrystal structures, carbon impurities can be introduced into the nanocrystal charge storage layers. The disclosed embodiments are useful for a variety of NVM cell types including split-gate NVM cells, floating gate NVM cells, discrete charge storage NVM cells, and/or other desired NVM cells. Advantageously, the carbon impurities introduce tensile stress into the cell structures, and this tensile stress helps maintain NVM system performance and data retention even as device geometries are reduced.

摘要翻译： 公开了具有碳杂质的非易失性存储器（NVM）单元以及相关的制造方法。 可以使用各种技术引入碳杂质，包括通过硅 - 碳（SiC）层和/或碳植入物的外延生长。 此外，可以将碳杂质引入NVM单元内的一个或多个结构，包括源极区，漏极区，栅极区和/或电荷存储层。 对于利用纳米晶体结构的离散电荷存储层，可将碳杂质引入纳米晶电荷存储层。 所公开的实施例对于包括分裂门NVM单元，浮动栅极NVM单元，分立电荷存储NVM单元和/或其它期望的NVM单元的各种NVM单元类型是有用的。 有利地，碳杂质将细胞结构中的拉伸应力引入，并且即使在减小器件几何形状的情况下，该拉伸应力有助于维持NVM系统性能和数据保持。

公开(公告)号：US08163609B2

公开(公告)日：2012-04-24

申请号：US12964727

申请日：2010-12-09

申请人： Cheong Min Hong ,  Sung-Taeg Kang

发明人： Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02601 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.

摘要翻译： 使用半导体衬底制造半导体器件的方法包括在半导体衬底上形成具有第一带能的第一绝缘层。 具有第二带能的第一半导体层形成在第一绝缘层上。 第一半导体层被退火以从第一半导体层形成多个第一电荷保持器球。 在多个第一电荷保持器球的每个电荷保持器球上形成第一保护膜。 在多个第一电荷保持器球上形成具有第三带能的第二半导体层。 第二半导体层被退火以在多个第一电荷保持器球上从第二半导体层形成多个存储小球。 第二带能量的大小在第一带能量的大小和第三带能量的大小之间。

公开(公告)号：US09112047B2

公开(公告)日：2015-08-18

申请号：US13779859

申请日：2013-02-28

申请人： Sung-Taeg Kang ,  Cheong Min Hong

发明人： Sung-Taeg Kang ,  Cheong Min Hong

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/66833

摘要： A split gate memory structure includes a pillar of active region having a first source/drain region disposed at a first end of the pillar, a second source/drain region disposed at a second end of the pillar, opposite the first end, and a channel region between the first and second source/drain regions. The pillar has a major surface extending between first and the second ends which exposes the first source/drain region, the channel region, and the second source/drain region. A select gate is adjacent the first source/drain region and a first portion of the channel region, wherein the select gate encircles the major surface the pillar. A charge storage layer is adjacent the second source/drain region and a second portion of the channel region, wherein the charge storage layer encircles the major surface the pillar. A control gate is adjacent the charge storage layer, wherein the control gate encircles the pillar.

摘要翻译： 分离栅极存储器结构包括具有设置在柱的第一端处的第一源极/漏极区域的有源区域的柱，设置在与第一端相对的柱的第二端处的第二源极/漏极区域，以及沟道 区域在第一和第二源极/漏极区域之间。 支柱具有在第一和第二端之间延伸的主表面，其暴露第一源极/漏极区域，沟道区域和第二源极/漏极区域。 选择栅极与第一源极/漏极区域和沟道区域的第一部分相邻，其中选择栅极围绕主表面支柱。 电荷存储层邻近第二源极/漏极区域和沟道区域的第二部分，其中电荷存储层围绕主表面柱。 控制栅极与电荷存储层相邻，其中控制栅极包围柱。

公开(公告)号：US20150069490A1

公开(公告)日：2015-03-12

申请号：US14022646

申请日：2013-09-10

申请人： Jane A. Yater ,  Cheong Min Hong ,  Sung-Taeg Kang

发明人： Jane A. Yater ,  Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L27/11568 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.

公开(公告)号：US08962416B1

公开(公告)日：2015-02-24

申请号：US13954205

申请日：2013-07-30

申请人： Brian A. Winstead ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Jane A. Yater

发明人： Brian A. Winstead ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Jane A. Yater

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.

摘要翻译： 制造半导体结构的方法使用具有第一类型的背景掺杂的衬底。 栅极结构在衬底上具有栅极电介质，栅极电介质上具有选择栅极层。 使用第二类型的掺杂剂，将与第一端相邻的衬底的第一部分进行植入。 在将任何掺杂剂注入到成为第二类型的第一掺杂区域的第一部分的背景掺杂之前，注入之前。 NVM栅极结构具有选择栅极，在第一掺杂区域上具有第一部分的存储层以及存储层上的控制栅极。 以与第一类型的掺杂剂非垂直的角度植入在选择栅极下形成深掺杂区域。 与第二种类型的掺杂剂一起植入形成源/漏扩展。

公开(公告)号：US08048738B1

公开(公告)日：2011-11-01

申请号：US12760313

申请日：2010-04-14

申请人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

发明人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/461

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.

摘要翻译： 一种形成半导体器件的方法包括在衬底上形成电介质层。 该方法还包括在电介质层上形成选择栅极层。 该方法还包括以第一蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第一部分，其中以第一蚀刻速率蚀刻选择栅极层的步骤包括使用氧化剂至少氧化 在介质层下面的衬底的顶部以形成氧化物层。 该方法还包括以低于第一蚀刻速率的第二蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第二部分，其中以第二蚀刻速率蚀刻选择栅极层的步骤包括仅去除 电介质层的顶部。

公开(公告)号：US20110256705A1

公开(公告)日：2011-10-20

申请号：US12760313

申请日：2010-04-14

申请人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

发明人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.

摘要翻译： 一种形成半导体器件的方法包括在衬底上形成电介质层。 该方法还包括在电介质层上形成选择栅极层。 该方法还包括以第一蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第一部分，其中以第一蚀刻速率蚀刻选择栅极层的步骤包括使用氧化剂至少氧化 在介质层下面的衬底的顶部以形成氧化物层。 该方法还包括以低于第一蚀刻速率的第二蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第二部分，其中以第二蚀刻速率蚀刻选择栅极层的步骤包括仅去除 电介质层的顶部。