公开(公告)号：US11664444B2

公开(公告)日：2023-05-30

申请号：US17205120

申请日：2021-03-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsu Ming Hsiao ,  Ming-Jhe Sie ,  Hsiu-Hao Tsao ,  Hong Pin Lin ,  Che-Fu Chen ,  An Chyi Wei ,  Yi-Jen Chen

IPC: H01L21/3105 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/31055 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468

Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

公开(公告)号：US11251085B2

公开(公告)日：2022-02-15

申请号：US16050028

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jie-Cheng Deng ,  Horng-Huei Tseng ,  Yi-Jen Chen

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/033 ,  H01L21/32 ,  H01L27/088 ,  H01L21/84 ,  H01L27/02 ,  H01L29/78

Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.

公开(公告)号：US20210376114A1

公开(公告)日：2021-12-02

申请号：US17205120

申请日：2021-03-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsu Ming Hsiao ,  Ming-Jhe Sie ,  Hsiu-Hao Tsao ,  Hong Pin Lin ,  Che-fu Chen ,  An Chyi Wei ,  Yi-Jen Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/3105

Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

公开(公告)号：US10804371B2

公开(公告)日：2020-10-13

申请号：US16050420

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Che-Cheng Chang ,  Sheng-Chi Shih ,  Yi-Jen Chen

IPC: H01L21/3213 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate.

公开(公告)号：US20180350949A1

公开(公告)日：2018-12-06

申请号：US16050420

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Che-Cheng Chang ,  Sheng-Chi Shih ,  Yi-Jen Chen

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/51

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate.

公开(公告)号：US20160005832A1

公开(公告)日：2016-01-07

申请号：US14851998

申请日：2015-09-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Che-Cheng Chang ,  Yi-Ren Chen ,  Chang-Yin Chen ,  Yi-Jen Chen ,  Ming Zhu ,  Yung-Jung Chang ,  Harry-Hak-Lay Chuang

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/517 ,  H01L21/02181 ,  H01L21/0234 ,  H01L21/28158 ,  H01L21/28185 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/321 ,  H01L21/32136 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: A device may include: a high-k layer disposed on a substrate and over a channel region in the substrate. The high-k layer may include a high-k dielectric material having one or more impurities therein, and the one or more impurities may include at least one of C, Cl, or N. The one or more impurities may have a molecular concentration of less than about 50%. The device may further include a cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate.

Abstract translation: 器件可以包括：高k层，其设置在衬底上并且在衬底中的沟道区域上方。 高k层可以包括其中具有一种或多种杂质的高k介电材料，并且一种或多种杂质可以包括C，Cl或N中的至少一种。一种或多种杂质可以具有 小于约50％。 器件还可以包括在沟道区域上的高k层上的覆盖层，高k层分离覆盖层和衬底。

公开(公告)号：US12165873B2

公开(公告)日：2024-12-10

申请号：US17739965

申请日：2022-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： En-Ping Lin ,  Yu-Ling Ko ,  I-Chung Wang ,  Yi-Jen Chen ,  Sheng-Kai Jou ,  Chih-Teng Liao

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/8238

Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.

公开(公告)号：US11264484B2

公开(公告)日：2022-03-01

申请号：US17068537

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Che-Cheng Chang ,  Sheng-Chi Shih ,  Yi-Jen Chen

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate.

公开(公告)号：US20230268427A1

公开(公告)日：2023-08-24

申请号：US18306769

申请日：2023-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsu Ming Hsiao ,  Ming-Jhe Sie ,  Hsiu-Hao Tsao ,  Hong Pin Lin ,  Che-fu Chen ,  An Chyi Wei ,  Yi-Jen Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/3105

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L21/31055 ,  H01L21/823468 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

公开(公告)号：US20230101838A1

公开(公告)日：2023-03-30

申请号：US18075172

申请日：2022-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jui Fu HSIEH ,  Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Jen Chen ,  Tzu-Chan Weng

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.