公开(公告)号：US20240274668A1

公开(公告)日：2024-08-15

申请号：US18645481

申请日：2024-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui Fu HSIEH ,  Chih-Teng LIAO ,  Chih-Shan CHEN ,  Yi-Jen CHEN ,  Tzu-Chan WENG

IPC: H01L29/08 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/32136 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.

公开(公告)号：US20230101838A1

公开(公告)日：2023-03-30

申请号：US18075172

申请日：2022-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jui Fu HSIEH ,  Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Jen Chen ,  Tzu-Chan Weng

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.

公开(公告)号：US20230411127A1

公开(公告)日：2023-12-21

申请号：US17842565

申请日：2022-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tai-Jung CHUANG ,  Chiao-Yuan HSIAO ,  Yung-Chan CHEN ,  Wei Kang CHUNG ,  Yu-Li LIN ,  Jui Fu HSIEH ,  Chih-Teng LIAO

IPC: H01J37/32 ,  H01L21/66 ,  H01L21/311

CPC classification number: H01J37/32807 ,  H01J37/32449 ,  H01L22/26 ,  H01L21/31116 ,  H01J2237/334 ,  H01J2237/24585

Abstract: Embodiments are directed to a method of operating a plasma processing system by retrofitting one or more components thereof. The method includes removing a holder from a gas supply mechanism of the plasma processing system. The holder includes a gas injector that is configured to provide gas received from a gas source to a plasma chamber of the plasma processing system. The method further includes reducing a size of a guide pin of the holder, installing the holder including the guide pin having the reduced size in the gas supply mechanism, and rotating the gas injector to change a flow of gas through the gas injector.

公开(公告)号：US20230387270A1

公开(公告)日：2023-11-30

申请号：US18232289

申请日：2023-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Chi YU ,  Jui Fu HSIEH ,  Yu-Li LIN ,  Chih-Teng LIAO ,  Yi-Jen CHEN

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/31111 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7851

Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

公开(公告)号：US20230352559A1

公开(公告)日：2023-11-02

申请号：US17661130

申请日：2022-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yan-Ting SHEN ,  Yu-Li LIN ,  Jui Fu HSIEH ,  Chih-Teng LIAO

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/66795

Abstract: A dummy gate structure may be formed for a semiconductor device. The dummy gate structure may be formed from an amorphous polysilicon layer. The amorphous polysilicon layer may be deposited in a blanket deposition operation. An annealing operation is performed for the semiconductor device to remove voids, seams, and/or other defects from the amorphous polysilicon layer. The annealing operation may cause the amorphous polysilicon layer to crystallize, thereby resulting in the amorphous polysilicon layer transitioning into a crystallized polysilicon layer. A dual radio frequency (RF) source etch technique may be performed to increase the directionality of ions and radicals in a plasma that is used to etch the crystallized polysilicon layer to form the dummy gate structure. The increased directionality of the ions increases the effectiveness of the ions in etching through the different crystal grain boundaries which increases the etch rate uniformity across the crystallized polysilicon layer.

公开(公告)号：US20220216324A1

公开(公告)日：2022-07-07

申请号：US17700034

申请日：2022-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Chi YU ,  Jui Fu HSIEH ,  Yu-Li LIN ,  Chih-Teng LIAO ,  Yi-Jen CHEN

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.