公开(公告)号：US20210272807A1

公开(公告)日：2021-09-02

申请号：US17321529

申请日：2021-05-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Chang ,  Li-Te Lin ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Pinyen Lin ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

摘要： A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

公开(公告)号：US10998421B2

公开(公告)日：2021-05-04

申请号：US16035844

申请日：2018-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49

摘要： A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US20230395504A1

公开(公告)日：2023-12-07

申请号：US17804919

申请日：2022-06-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu Pei Chen ,  Chia-Hao Chang ,  Shin-Yi Yang ,  Chia-Hung Chu ,  Po-Chin Chang ,  Shuen-Shin Liang ,  Chun-Hung Liao ,  Yuting Cheng ,  Hung-Yi Huang ,  Harry Chien ,  Pinyen Lin ,  Sung-Li Wang

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76843

摘要： Provided are devices with conductive contacts and methods for forming such devices. A method includes forming a lower conductive contact in a dielectric material and over a structure, wherein the lower conductive contact has opposite sidewalls that extend to and terminate at a top surface. The method also includes separating an upper portion of each sidewall from the dielectric material and locating a barrier material between the upper portion of each sidewall and the dielectric material. Further, the method includes forming an upper conductive contact over the lower conductive contact.

公开(公告)号：US09520482B1

公开(公告)日：2016-12-13

申请号：US14940841

申请日：2015-11-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Chang ,  Chih-Hao Wang ,  Kai-Chieh Yang ,  Shih-Ting Hung ,  Wei-Hao Wu ,  Gloria Wu ,  Inez Fu ,  Chia-Wei Su ,  Yi-Hsuan Hsiao

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L27/092

CPC分类号： H01L29/66545 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924

摘要： A method for fabricating a semiconductor device includes forming a first fin and a second fin on a substrate. The first fin has a first gate region and the second fin has a second gate region. The method also includes forming a metal-gate line over the first and second gate regions. The metal-gate line extends from the first fin to the second fin. The method also includes applying a line-cut to separate the metal-gate line into a first sub-metal gate line and a second sub-metal gate line and forming an isolation region within the line cut.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成第一鳍片和第二鳍片。 第一鳍片具有第一栅极区域，第二鳍片具有第二栅极区域。 该方法还包括在第一和第二栅极区域上形成金属栅极线。 金属栅极线从第一鳍延伸到第二鳍。 该方法还包括施加线切割以将金属栅极线分离成第一子金属栅极线和第二子金属栅极线并在线切割中形成隔离区。

公开(公告)号：US11862465B2

公开(公告)日：2024-01-02

申请号：US17589315

申请日：2022-01-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Chun Huang ,  Chiu-Hsiang Chen ,  Ya-Wen Yeh ,  Yu-Tien Shen ,  Po-Chin Chang ,  Chien-Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC分类号： H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115

CPC分类号： H01L21/0338 ,  H01L21/0217 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155

摘要： A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

公开(公告)号：US20240021673A1

公开(公告)日：2024-01-18

申请号：US17864372

申请日：2022-07-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Lin-Yu Huang ,  Po-Chin Chang

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L23/528 ,  H01L23/522 ,  H01L29/08 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

CPC分类号： H01L29/0673 ,  H01L29/42392 ,  H01L23/5283 ,  H01L23/5226 ,  H01L29/0847 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439

摘要： A semiconductor device includes two source/drain features, a gate structure, a first contact plug, a second contact plug, a conductive line, and a nitride capping layer. The two source/drain features are laterally arranged to each other. The one or more channel layers connects the two source/drain features. The gate structure engages the one or more channel layers and interposes the two source/drain features. The first contact plug extends from above a first source/drain feature of the two source/drain features to the first source/drain feature. The second contact plug extends from below a second source/drain feature of the two source/drain features to the second source/drain feature. The conductive line is disposed underneath the second contact plug and electrically coupled to the second contact plug. The nitride capping layer is disposed between the second contact plug and the conductive line.

公开(公告)号：US20200020785A1

公开(公告)日：2020-01-16

申请号：US16035844

申请日：2018-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/8234

摘要： A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US20240096997A1

公开(公告)日：2024-03-21

申请号：US18097249

申请日：2023-01-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Chin Chang ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Yuting Cheng ,  Sung-Li Wang ,  Pinyen Lin

IPC分类号： H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC分类号： H01L29/45 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

摘要： Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed in a PFET region and a second source/drain region disposed in an NFET region. The second source/drain region comprises a dipole region. The structure further includes a first silicide layer disposed on and in contact with the first source/drain region, a second silicide layer disposed on and in contact with the first silicide layer, and a third silicide layer disposed on and in contact with the dipole region of the second source/drain region. The first, second, and third silicide layers include different materials. The structure further includes a first conductive feature disposed over the first source/drain region, a second conductive feature disposed over the second source/drain region, and an interconnect structure disposed on the first and second conductive features.

公开(公告)号：US11881401B2

公开(公告)日：2024-01-23

申请号：US17321529

申请日：2021-05-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Chang ,  Li-Te Lin ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Pinyen Lin ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L21/0337 ,  H01L21/0228 ,  H01L21/02118 ,  H01L21/31116 ,  H01L21/76877

摘要： A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

公开(公告)号：US11651972B2

公开(公告)日：2023-05-16

申请号：US17403850

申请日：2021-08-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ya-Wen Yeh ,  Yu-Tien Shen ,  Shih-Chun Huang ,  Po-Chin Chang ,  Wei-Liang Lin ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu

IPC分类号： H01L21/321 ,  H01L21/3213 ,  H01L21/66

CPC分类号： H01L21/32137 ,  H01L21/32139 ,  H01L22/12 ,  H01L22/26

摘要： In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.