公开(公告)号：US20240363756A1

公开(公告)日：2024-10-31

申请号：US18737644

申请日：2024-06-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Lien Huang ,  Yi-Shan Chen ,  Kuan-Da Huang ,  Han-Yu Lin ,  Li-Te Lin ,  Ming-Huan Tsai

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/417

CPC分类号： H01L29/785 ,  H01L29/401 ,  H01L29/41791

摘要： A semiconductor device includes: a semiconductor fin extending along a first lateral direction; a gate structure extending along a second lateral direction perpendicular to the first lateral direction and straddling the semiconductor fin; an epitaxial structure disposed in the semiconductor fin and next to the gate structure; a first interconnect structure extending along the second lateral direction and disposed above the epitaxial structure; and a dielectric layer including a first portion and a second portion that form a stair.

公开(公告)号：US11973129B2

公开(公告)日：2024-04-30

申请号：US18182774

申请日：2023-03-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Han-Yu Lin ,  Chansyun David Yang ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/6681 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31116 ,  H01L21/32105 ,  H01L21/3211 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.

公开(公告)号：US20210272807A1

公开(公告)日：2021-09-02

申请号：US17321529

申请日：2021-05-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Chang ,  Li-Te Lin ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Pinyen Lin ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

摘要： A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

公开(公告)号：US10998421B2

公开(公告)日：2021-05-04

申请号：US16035844

申请日：2018-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49

摘要： A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US10861953B2

公开(公告)日：2020-12-08

申请号：US15966603

申请日：2018-04-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Lun Chen ,  Chao-Hsien Huang ,  Li-Te Lin ,  Chun-Hsiung Lin

IPC分类号： H01L21/8234 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

摘要： A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.

公开(公告)号：US20230067696A1

公开(公告)日：2023-03-02

申请号：US17461779

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Lien Huang ,  Yi-Shan Chen ,  Kuan-Da Huang ,  Han-Yu Lin ,  Li-Te Lin ,  Ming-Huan Tsai

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/40

摘要： A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.

公开(公告)号：US20200020785A1

公开(公告)日：2020-01-16

申请号：US16035844

申请日：2018-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/8234

摘要： A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US12002663B2

公开(公告)日：2024-06-04

申请号：US17377601

申请日：2021-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Rung Hsu ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01J37/32 ,  H01L21/3065 ,  H01L21/311

CPC分类号： H01J37/32743 ,  H01J37/3211 ,  H01J37/32449 ,  H01L21/3065 ,  H01L21/31116 ,  H01J37/32568

摘要： A processing apparatus is provided. The processing apparatus includes a chamber and a carrier that is positioned in the chamber for holding a substrate. The processing apparatus further includes a gas inlet connected to the chamber. The gas inlet is configured to supply a process gas into the chamber. The processing apparatus also includes a coil module positioned around the chamber and configured to transfer the process gas into plasma. In addition, the processing apparatus includes a filter disposed in the chamber. The coil module is configured to change a position of the plasma between a first position and a second position, the first position is located between the gas inlet and the filter, and the second position is located between the filter and the carrier.

公开(公告)号：US11942372B2

公开(公告)日：2024-03-26

申请号：US17459065

申请日：2021-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Da Huang ,  Hao-Heng Liu ,  Li-Te Lin

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/088

CPC分类号： H01L21/823475 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0207 ,  H01L27/088

摘要： In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions. A lower inter-level dielectric (ILD) layer is formed over the pair of source/drain regions and around the gate electrode. A gate capping layer is formed over the gate electrode. A selective etch and deposition process is performed to form a dielectric protection layer on the gate capping layer while forming a contact opening within the lower ILD layer. A lower source/drain contact is formed within the contact opening.

公开(公告)号：US11908701B2

公开(公告)日：2024-02-20

申请号：US17238170

申请日：2021-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Christine Y Ouyang ,  Li-Te Lin

IPC分类号： H01L21/311 ,  H01L21/02 ,  H01L21/768

CPC分类号： H01L21/31116 ,  H01L21/02118 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76895

摘要： A patterning method includes at least the following steps. A first material layer is provided. A second material layer is provided over the first material layer. The second material layer partially exposes the first material layer. A passivation layer is formed over the first material layer and the second material layer. A growth rate of the passivation layer on the second material layer is greater than a growth rate of the passivation layer on the first material layer. A first etching process is performed to remove a portion of the passivation layer and a portion of the first material layer.