公开(公告)号：US20200020785A1

公开(公告)日：2020-01-16

申请号：US16035844

申请日：2018-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/8234

摘要： A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US11973129B2

公开(公告)日：2024-04-30

申请号：US18182774

申请日：2023-03-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Han-Yu Lin ,  Chansyun David Yang ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/6681 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31116 ,  H01L21/32105 ,  H01L21/3211 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.

公开(公告)号：US20240055501A1

公开(公告)日：2024-02-15

申请号：US17887487

申请日：2022-08-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pinyen Lin ,  Chung-Liang Cheng ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Huang-Lin Chao

IPC分类号： H01L29/45 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/285 ,  H01L29/66

CPC分类号： H01L29/45 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/28518 ,  H01L29/66742 ,  H01L29/66439

摘要： A semiconductor device and the manufacturing method thereof are described. The device includes semiconductor channel sheets, source and drain regions and a gate structure. The semiconductor channel sheets are arranged in parallel and spaced apart from one another. The source and drain regions are disposed beside the semiconductor channel sheets. The gate structure is disposed around and surrounding the semiconductor channel sheets. The silicide layer is disposed on the source region or the drain region. A contact structure is disposed on the silicide layer on the source region or the drain region. The contact structure includes a metal contact and a liner, and the silicide layer is in contact with the metal contact, and the liner is separate from the silicide layer by the metal contact.

公开(公告)号：US20210272807A1

公开(公告)日：2021-09-02

申请号：US17321529

申请日：2021-05-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Chang ,  Li-Te Lin ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Pinyen Lin ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

摘要： A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

公开(公告)号：US10998421B2

公开(公告)日：2021-05-04

申请号：US16035844

申请日：2018-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49

摘要： A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US12002663B2

公开(公告)日：2024-06-04

申请号：US17377601

申请日：2021-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Rung Hsu ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01J37/32 ,  H01L21/3065 ,  H01L21/311

CPC分类号： H01J37/32743 ,  H01J37/3211 ,  H01J37/32449 ,  H01L21/3065 ,  H01L21/31116 ,  H01J37/32568

摘要： A processing apparatus is provided. The processing apparatus includes a chamber and a carrier that is positioned in the chamber for holding a substrate. The processing apparatus further includes a gas inlet connected to the chamber. The gas inlet is configured to supply a process gas into the chamber. The processing apparatus also includes a coil module positioned around the chamber and configured to transfer the process gas into plasma. In addition, the processing apparatus includes a filter disposed in the chamber. The coil module is configured to change a position of the plasma between a first position and a second position, the first position is located between the gas inlet and the filter, and the second position is located between the filter and the carrier.

公开(公告)号：US20240105500A1

公开(公告)日：2024-03-28

申请号：US18106680

申请日：2023-02-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kenichi Sano ,  Chin-Hsiang Lin ,  Hsu-Kai Chang ,  Pinyen Lin

IPC分类号： H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/088

CPC分类号： H01L21/76229 ,  H01L21/76883 ,  H01L21/823878 ,  H01L27/088

摘要： The present disclosure provides a method for repairing a seam within a conformally deposited material. One or more seam repairing precursor sources may be delivered to seams or voids using a carrier at a super critical fluid phase. At the super critical fluid phase, the carrier has liquid like density and gas like high diffusion capability, therefore capable of delivering the repairing precursor sources to seams or voids under surfaces of a structure. In some embodiments, carbon dioxide or argon may be used as a carrier.

公开(公告)号：US11862465B2

公开(公告)日：2024-01-02

申请号：US17589315

申请日：2022-01-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Chun Huang ,  Chiu-Hsiang Chen ,  Ya-Wen Yeh ,  Yu-Tien Shen ,  Po-Chin Chang ,  Chien-Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC分类号： H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115

CPC分类号： H01L21/0338 ,  H01L21/0217 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155

摘要： A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

公开(公告)号：US20230389335A1

公开(公告)日：2023-11-30

申请号：US18446557

申请日：2023-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Liang Liu ,  Sheng-Chau Chen ,  Chung-Liang Cheng ,  Chia-Shiung Tsai ,  Yeong-Jyh Lin ,  Pinyen Lin ,  Huang-Lin Chao

IPC分类号： H10B61/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L29/786

CPC分类号： H10B61/22 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/66553 ,  H01L29/66545 ,  H01L29/78696

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

公开(公告)号：US11581222B2

公开(公告)日：2023-02-14

申请号：US17018356

申请日：2020-09-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Jui Huang ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a source/drain contact structure formed over a substrate. A first gate spacer is separated the gate stack from the source/drain contact structure and extends above top surfaces of the gate stack and the source/drain contact structure. An insulating capping layer covers the top surface of the gate stack and extends on the top surface of the first gate spacer. A conductive via structure partially covers the top surface of the insulating capping layer and the top surface of the source/drain contact structure. A first insulating layer surrounds the conductive via structure and partially covers the top surface of the source/drain contact structure.