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公开(公告)号：US11616067B2
公开(公告)日：2023-03-28
申请号：US17552433
申请日：2021-12-16
Inventor： Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Chin-Yuan Tseng , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Wei-Liang Lin , L. C. Chou
IPC: H01L21/8234 , H01L27/11 , H01L27/088 , H01L21/308 , H01L29/78 , H01L29/66 , H01L21/311
Abstract: In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.
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2.发明申请公开(公告)号：US20220223428A1
公开(公告)日：2022-07-14
申请号：US17705615
申请日：2022-03-28
Inventor： Chi-Cheng Hung , Chun-Kuang Chen , De-Fang Chen , Wei-Liang Lin , Yu-Tien Shen
IPC: H01L21/308 , H01L21/027 , H01L21/31 , H01L21/311 , H01L21/033 , H01L21/306 , H01L21/3065
Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.
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公开(公告)号：US20210272807A1
公开(公告)日：2021-09-02
申请号：US17321529
申请日：2021-05-17
Inventor： Po-Chin Chang , Li-Te Lin , Ru-Gun Liu , Wei-Liang Lin , Pinyen Lin , Yu-Tien Shen , Ya-Wen Yeh
IPC: H01L21/033 , H01L21/311 , H01L21/768 , H01L21/02
Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.
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公开(公告)号：US10146141B2
公开(公告)日：2018-12-04
申请号：US14471653
申请日：2014-08-28
Inventor： Chi-Cheng Hung , Wei-Liang Lin , Yung-Sung Yen , Chun-Kuang Chen , Ru-Gun Liu , Tsai-Sheng Gau , Tzung-Chi Fu , Ming-Sen Tung , Fu-Jye Liang , Li-Jui Chen , Meng-Wei Chen , Kuei-Shun Chen
IPC: G03F7/20
Abstract: The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.
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公开(公告)号：US20180286698A1
公开(公告)日：2018-10-04
申请号：US15996099
申请日：2018-06-01
Inventor： Chin-Yuan Tseng , Chi-Cheng Hung , Chun-Kuang Chen , De-Fang Chen , Ru-Gun Liu , Tsai-Sheng Gau , Wei-Liang Lin
IPC: H01L21/311 , H01L21/033
CPC classification number: H01L21/31144 , H01L21/0337
Abstract: Patterning techniques are disclosed that can relax overlay requirements and/or increase integrated circuit design flexibility. An exemplary method includes forming a first set of fins and a second set of fins having different etch sensitivities on a material layer. The fins of the second set of fins are interspersed between the fins of the first set of fins. A first patterning process removes a subset of the first set of fins and a portion of the material layer underlying the subset of the first set of fins. The first patterning process avoids substantial removal of an exposed portion of the second set of fins. A second patterning process removes a subset of the second set of fins and a portion of the material layer underlying the subset of the second set of fins. The second patterning process avoids substantial removal of an exposed portion of the first set of fins.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11901188B2
公开(公告)日：2024-02-13
申请号：US17705615
申请日：2022-03-28
Inventor： Chi-Cheng Hung , Chun-Kuang Chen , De-Fang Chen , Wei-Liang Lin , Yu-Tien Shen
IPC: H01L21/308 , H01L21/027 , H01L21/31 , H01L21/311 , H01L21/033 , H01L21/306 , H01L21/3065 , G03F7/00
CPC classification number: H01L21/3086 , H01L21/027 , H01L21/0274 , H01L21/0332 , H01L21/0337 , H01L21/308 , H01L21/3065 , H01L21/3081 , H01L21/3085 , H01L21/3088 , H01L21/30604 , H01L21/31 , H01L21/31144 , G03F7/0035
Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.
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公开(公告)号：US20240019787A1
公开(公告)日：2024-01-18
申请号：US18223993
申请日：2023-07-19
Inventor： Ru-Gun LIU , Huicheng Chang , Chia-Cheng Chen , Jyu-Horng Shieh , Liang-Yin Chen , Shu-Huei Suen , Wei-Liang Lin , Ya Hui Chang , Yi-Nien Su , Yung-Sung Yen , Chia-Fong Chang , Ya-Wen Yeh , Yu-Tien Shen
CPC classification number: G03F7/70558 , H01L21/0274 , G03F7/70033 , G03F7/70625 , G03F1/22 , G03F1/36 , G03F1/70 , G03F7/0035 , G03F7/40
Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
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公开(公告)号：US11222899B2
公开(公告)日：2022-01-11
申请号：US16918798
申请日：2020-07-01
Inventor： Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Chin-Yuan Tseng , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Wei-Liang Lin , L. C. Chou
IPC: H01L27/11 , H01L21/8234 , H01L27/088 , H01L21/308 , H01L29/78 , H01L29/66 , H01L21/311
Abstract: A semiconductor device including fins arranged so that: in a situation in which any given first one of the fins (first given fin) is immediately adjacent any given second one of the fins (second given fin), and subject to fabrication tolerance, there is a minimum gap, Gmin, between the first and second given fins; and the first and second given fins a minimum pitch, Pmin, that falls in a range as follows: (Gmin+(≈90%)*T1)≤Pmin≤(Gmin+(≈110%)*T1).
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公开(公告)号：US10074657B2
公开(公告)日：2018-09-11
申请号：US15362002
申请日：2016-11-28
Inventor： Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Chin-Yuan Tseng , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Wei-Liang Lin , L. C. Chou
IPC: H01L21/30 , H01L27/11 , H01L21/8234 , H01L27/088 , H01L21/308
CPC classification number: H01L27/1104 , H01L21/3083 , H01L21/3086 , H01L21/31144 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/7851
Abstract: A method, of manufacturing fins for a semiconductor device which includes Fin-FETs, includes: forming a structure including a semiconductor substrate and capped semiconductor fins, the capped semiconductor fins being organized into at least first and second sets, with each member of the first set having a first cap with a first etch sensitivity, and each member of the second set having a second cap with a second etch, the second etch sensitivity being different than the first etch sensitivity; removing selected members of the first set and selected members of the second set from the structure.
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公开(公告)号：US09991132B2
公开(公告)日：2018-06-05
申请号：US14689288
申请日：2015-04-17
Inventor： Chin-Yuan Tseng , Chi-Cheng Hung , Chun-Kuang Chen , De-Fang Chen , Ru-Gun Liu , Tsai-Sheng Gau , Wei-Liang Lin
IPC: H01L21/00 , H01L21/311 , H01L21/033
CPC classification number: H01L21/31144 , H01L21/0337
Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a workpiece having a material layer disposed on a substrate. A first set of fins is formed on the material layer, and a second set of fins is formed on the material layer interspersed between the first set of fins. The second set of fins have a different etchant sensitivity from the first set of fins. A first etching process is performed on the first set of fins and configured to avoid substantial etching of the second set of fins. A second etching process is performed on the second set of fins and configured to avoid substantial etching of the first set of fins. The material layer is etched to transfer a pattern defined by the first etching process and the second etching process.
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