公开(公告)号：US10269624B2

公开(公告)日：2019-04-23

申请号：US15801154

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xi-Zong Chen ,  Y. H. Kuo ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/28 ,  H01L23/538 ,  H01L27/088 ,  H01L29/417 ,  H01L21/027

Abstract: An embodiment method includes patterning an opening through a dielectric layer, depositing an adhesion layer along sidewalls and a bottom surface of the opening, depositing a first mask layer in the opening over the adhesion layer, etching back the first mask layer below a top surface of the dielectric layer, and widening an upper portion of the opening after etching back the first mask layer. The first mask layer masks a bottom portion of the opening while widening the upper portion of the opening. The method further includes removing the first mask layer after widening the upper portion of the opening and after removing the first mask layer, forming a contact in the opening by depositing a conductive material in the opening over the adhesion layer.

公开(公告)号：US20190006236A1

公开(公告)日：2019-01-03

申请号：US16045073

申请日：2018-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Tsang Hsieh ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/475 ,  H01L23/528 ,  H01L21/4757 ,  H01L29/06

Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

公开(公告)号：US09230854B2

公开(公告)日：2016-01-05

申请号：US13963731

申请日：2013-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cha-Hsin Chao ,  Chih-Hao Chen ,  Hsin-Yi Tsai

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/53295 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.

Abstract translation: 提供了一种用于半导体器件的系统和方法。 一个实施例包括电介质层，电介质层上的硬掩模层和硬掩模层上的覆盖层。 执行多图案化工艺以形成使用覆盖层作为掩模的互连，以形成用于互连的开口。

公开(公告)号：US20240395508A1

公开(公告)日：2024-11-28

申请号：US18323769

申请日：2023-05-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao Chen ,  Chung Chuan Huang ,  Yi-Tsang Hsieh ,  Yu-Chi Lin ,  Cha-Hsin Chao ,  Che-En Tsai

IPC: H01J37/32

Abstract: A semiconductor manufacturing apparatus for performing a process is disclosed. An apparatus includes a chamber configured to receive a wafer for an etching process; a conductive focus ring disposed within the chamber and configured to focus an electric field to control an etch direction of the etching process; and an insulative cover ring disposed within the chamber, wherein the insulative cover ring is configured to modify the electric field, wherein the insulative cover ring has an inner annular insulative portion and outer annular insulative portion, and wherein a gap is defined between the inner annular insulative portion and the outer annular insulative portion.

公开(公告)号：US20190252245A1

公开(公告)日：2019-08-15

申请号：US16390735

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xi-Zong Chen ,  Y.H. Kuo ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC: H01L21/768 ,  H01L27/088 ,  H01L23/538 ,  H01L21/28 ,  H01L21/033 ,  H01L29/417 ,  H01L21/027

CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/28 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/5386 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795

Abstract: An embodiment method includes patterning an opening through a dielectric layer, depositing an adhesion layer along sidewalls and a bottom surface of the opening, depositing a first mask layer in the opening over the adhesion layer, etching back the first mask layer below a top surface of the dielectric layer, and widening an upper portion of the opening after etching back the first mask layer. The first mask layer masks a bottom portion of the opening while widening the upper portion of the opening. The method further includes removing the first mask layer after widening the upper portion of the opening and after removing the first mask layer, forming a contact in the opening by depositing a conductive material in the opening over the adhesion layer.

公开(公告)号：US20190035679A1

公开(公告)日：2019-01-31

申请号：US15801154

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd

Inventor： Xi-Zong Chen ,  Y.H. Kuo ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/538 ,  H01L27/088 ,  H01L21/28

Abstract: An embodiment method includes patterning an opening through a dielectric layer, depositing an adhesion layer along sidewalls and a bottom surface of the opening, depositing a first mask layer in the opening over the adhesion layer, etching back the first mask layer below a top surface of the dielectric layer, and widening an upper portion of the opening after etching back the first mask layer. The first mask layer masks a bottom portion of the opening while widening the upper portion of the opening. The method further includes removing the first mask layer after widening the upper portion of the opening and after removing the first mask layer, forming a contact in the opening by depositing a conductive material in the opening over the adhesion layer.

公开(公告)号：US20190103281A1

公开(公告)日：2019-04-04

申请号：US16028496

申请日：2018-07-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xi-Zong Chen ,  Yun-Yu Hsieh ,  Cha-Hsin Chao ,  Li-Te Hsu

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311

Abstract: A method includes forming a mask layer over a target layer. A first etching process is performed on the mask layer to form a first opening and a second opening in the mask layer. A second etching process is performed on the mask layer to reduce an end-to-end spacing between the first opening and the second opening. The first etching process and the second etching process have different anisotropy properties. A pattern of the mask layer is transferred to the target layer.

公开(公告)号：US20190097038A1

公开(公告)日：2019-03-28

申请号：US16201266

申请日：2018-11-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xi-Zong Chen ,  Te-Chih Hsiung ,  Cha-Hsin Chao ,  Yi-Wei Chiu

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L23/535 ,  H01L21/321 ,  H01L21/311 ,  H01L21/027 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/3105

Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

公开(公告)号：US10049983B2

公开(公告)日：2018-08-14

申请号：US14987217

申请日：2016-01-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cha-Hsin Chao ,  Chih-Hao Chen ,  Hsin-Yi Tsai

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522

Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.

公开(公告)号：US20180174904A1

公开(公告)日：2018-06-21

申请号：US15386952

申请日：2016-12-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Tsang Hsieh ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/4757 ,  H01L21/475 ,  H01L23/528 ,  H01L29/06

Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.